Jaw-Jung Shin

A 65nm node strained SOI technology with slim spacer

A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current.

Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography

For the first time, a novel hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm thick SiON gate dielectric has been developed for advanced SOC applications. 26% (for N-FET) and 35% (for P-FET) improvements of intrinsic gate delay (CV/I) at low gate leakage of 20-40A/cm/sup 2/ have been achieved over previous leading-edge 45nm node version, while maintaining the same sub-threshold leakage (100nA//spl mu/m). 10 times reduction of the leakage can be further modulated by a virtual back-gate control. Fine patterning with line pitch of 90nm by immersion lithography is demonstrated, which features 0.183/spl mu/m/sup 2/ 6T-SRAM cell for 32nm node on-trend scaling.

Mask cost and cycle time reduction

In the IC industry the mask cost and cycle time have increased dramatically since the chip design has become more complex and the required mask specification, tighter. The lithography technology has been driven to 65-nm node and 90-nm product will be manufacturing in 2004, according to ITRSs roadmap. However, the optical exposure tools do not extend to a shorter wavelength as the critical dimension (CD) shrinks. In such sub-wavelength technology generation, the mask error factor (MEF) is normally higher. Higher MEF means that tighter mask specification is required to sustain the lithography performance. The tighter mask specification will impact both mask processing complexity and cost. The mask is no longer a low-cost process. In addition, the number of wafers printed from each mask set is trending down, resulting in a huge investment to tape out a new circuit. Higher cost discourages circuit shrinking, thus, prohibits commercialization of new technology nodes.

The REBL DPG: recent innovations and remaining challenges

Reflective electron-beam lithography (REBL) employs a novel device to impress pattern information on an electron beam. This device, the digital pattern generator (DPG), is an array of small electron reflectors, in which the reflectance of each mirror is controlled by underlying CMOS circuitry. When illuminated by a beam of low-energy electrons, the DPG is effectively a programmable electron-luminous image source. By switching the mirror drive circuits appropriately, the DPG can ‘scroll’ the image of an integrated circuit pattern across its surface; and the moving electron image, suitably demagnified, can be used to expose the resist-coated surface of a wafer or mask. This concept was first realized in a device suitable for 45 nm lithography demonstrations. A next-generation device has been designed and is presently nearing completion. The new version includes several advances intended to make it more suitable for application in commercial lithography systems. We will discuss the innovations and compromises in the design of this next-generation device. For application in commercially-practical maskless lithography at upcoming device nodes, still more advances will be needed. Some of the directions in which this technology can be extended will be described.

45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell

The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 /spl mu/m/sup 2/. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at 1V/0.85V with excellent drive currents of 1000/740 and 530/420 /spl mu/A//spl mu/m for N-FET and P-FET, respectively. The P-FET current is the best reported so far.

Study of mask corner rounding effects on lithographic patterning for 90-nm technology node and beyond

This paper presented an integrated simulation framework linking our in-house mask writer simulator and the optical lithography simulation engines to include the mask corner rounding effect in lithographic performance evaluations. In the writer simulator, a modified two-dimensional Gaussian function is used as the functional form of the convolution kernel (point spread function). Parameters of the kernel function for different writing machines are automatically extracted from scanning electron microscope (SEM) photographs of simple mask pattern geometries. The convolution results of the kernel and the mask layout form the intensity distribution for pattern definition. The isocontour of the resulting image at the desired level of bias can be regarded as a good approximation of the mask shape obtained from a real mask writer. The writer simulator then saves the contour data as the user-specified format of mask file for subsequent lithography simulations. With the aid of this simulation tool, the impacts of mask corner rounding effects on two-dimensional OPCed pattern for 90-nm and 65-nm node lithography processes are quantitatively evaluated. The results show the line end shortening (LES) is greatly influenced by mask corner rounding effects. The LESs in the 65-nm node process are over twice of those in the 90-nm node process. The resolution capability of a 2-stage 16X mask manufacturing process was also studied in this paper. Simulation results indicate the ArF lithography might be required to make this innovative mask-making technology suitable for 90-nm generation and beyond.

Influence of massively parallel e-beam direct-write pixel size on electron proximity correction

Massively E-beam maskless lithography (MEBML2) is one of the potential solutions for 32-nm half-pitch and beyond. In the past, its relatively low throughput restricted EBDW development to mostly mask making, small volume wafer production and prototyping. Recently the production worthy ML2 approaches, >10,000 e-beams writing in parallel, have been proposed by MAPPER, KLA and IMS. These approaches use raster scan in pattern writing. Hence the bitmap is certainly the final data format. The bitmap format used to have huge data volume with fine pixel size to maintain the CD accuracy after electron proximity correction (EPC). Data handling becomes necessary, especially on data transmission rate. The aggregated data transmission rate would be up to 1963 Tera bits per second (bps) for a 10 WPH tool using 1-nm pixel size and 1-bit gray level. It needs 19,630 fibers each transmitting 10 Gbps. The data rate per beam would be >20 Gbps in 10,000-beam MEBML2. Hence data reduction using bigger pixel size to achieve sub-nm EPC accuracy is crucial for reducing the fiber number to the beam number. In this paper, the writing-error-enhanced-factor to quantitatively characterize the impact of CD accuracy by various total blur in resist is reported; and we propose the vernier pattern to verify sub-nm CD accuracy and the in-house dithering raster method to achieve sub-0.2-nm CD accuracy using multiple-nm pixel sizes, which could reduce the need of the aggregated data rate to 11%, 33%, 44% and 79% of 1963 Tbps on 22-nm, 16-nm, 11-nm, 8-nm node respectively.

Mask error tensor and causality of mask error enhancement for low- k 1 imaging: theory and experiments

Three important concepts about the mask error enhancement factor (MEEF) are proposed. From the definition of MEEF, it could be derived as a function of the image log slope and the aerial image variation caused by mask critical dimension (CD) errors. Second, a mask error common window indicator (MECWIN) is proposed to evaluate the MEEF and mask CD specification by knowing the wafer CD tolerance. This concept is used to define the mask CD specification without any ambiguity. Finally, we describe the complex 2-D response to the mask-making error around the line end by a mask error enhancement tensor. Both theoretical derivations and experiments to justify the theory are presented.

REBL DPG lenslet structure: design for charging prevention

KLA-Tencor is currently developing Reflective Electron Beam Lithography (REBL), targeted as a production worthy multiple electron beam tool for next generation high volume lithography. The Digital Pattern Generator (DPG) integrated with CMOS and MEMS lenslets is a critical part of REBL. Previously, KLA-Tencor reported on progress towards a REBL tool for maskless lithography below the 10 nm technology node. However, the MEMS lenslet structure suffered from charging up during writing, requiring the usage of a charge drain coating. Since then, the TSMC multiple e-beam team and the KLA-Tencor REBL team have worked together to further develop the DPG for direct write lithography. In this paper, we introduce a hollow-structure MEMS lenslet array that inherently prevents charging during writing, and preliminary verification results are also presented.

Influence of data volume and EPC on process window in massively parallel e-beam direct write

Multiple e-beam direct write lithography (MEBDW), using >10,000 e-beams writing in parallel, proposed by MAPPER, KLA-Tencor, and IMS is a potential solution for 20-nm half-pitch and beyond. The raster scan in MEBDW makes bitmap its data format. Data handling becomes indispensable since bitmap needs a huge data volume due to the fine pixel size to keep the CD accuracy after e-beam proximity correction (EPC). In fact, in 10,000-beam MEBDW, for a 10 WPH tool of 1-nm pixel size and 1-bit gray level, the aggregated data transmission rate would be up to 1963 Tera bits per second (bps), requiring 19,630 fibers transmitting 10 Gbps in each fiber. The data rate per beam would be <20 Gbps. Hence data reduction using bigger pixel size, fewer grey levels to achieve sub-nm EPC accuracy, and data truncation have been extensively studied. In this paper, process window assessment through Exposure-Defocus (E-D) Forest to quantitatively characterize the data truncation before and after EPC is reported. REBL electron optics, electron scattering in resist, and resist acid diffusion are considered, to construct the E-D Forest and to analyze the imaging performance of the most representative layers and patterns, such as critical line/space and hole layers with minimum pitch, cutting layers, and implant layers, for the 10-nm, and 7-nm nodes.