Shyam Pal

Metal wiring critical dimension shrink using ALD spacer in BEOL sub-50nm pitch

In advanced technology nodes, the BEOL requires advanced patterning techniques such as triple patterning (LELELE) and side wall image transfer techniques to form metal and via structures with pitches below 50nm. In this paper, we demonstrate metal critical dimension (CD) shrinkage using atomic layer deposition (ALD) enabled spacer layer to achieve sub-50 nm pitch. ALD spacer thickness is identified as the crucial parameter to achieve target CD. An optimization study correlating oxide thickness, final CD and electrical yield is presented. An optimized recipe that results in 50% shrinkage is identified with good electrical yield.

Investigation of trench and contact hole shrink mechanism in the negative tone develop process

The objective of this work was to study the trench and contact hole shrink mechanism in negative tone develop resist processes and its manufacturability challenges associated for 20nm technology nodes and beyond. Process delay from post-exposure to develop, or “queue time”, is studied in detail. The impact of time link delay on resolved critical dimension (CD) is fully characterized for patterned resist and etched geometries as a function of various process changes. In this study, we assembled a detailed, theoretical model and performed experimental work to correlated time link delay to acid diffusion within the resist polymer matrix. Acid diffusion is determined using both a modulation transfer function for diffusion and simple approximation based on Fick’s law of diffusion.

Advancement in resist materials for sub-7 nm patterning and beyond

The rapid development in dense integrated circuits requires significant advancement in small scaling patterning technology. EUV technology is considered as a powerful solution for the sub-7 nm node pattering and beyond. The high performance resist development is required for the practical applications of the EUV patterning for high volume manufacturing. In the current work, the requirements for the development of next generation resist materials is reviewed and summarized to propose the design criterion for high performance photoresist materials.

High throughput and dense sampling metrology for process control

Optical metrology tool, LX530, is designed for high throughput and dense sampling metrology in semiconductor manufacture. It can inspect the dose and focus variation in the process control based on the critical dimension (CD) and line edge roughness (LER) measurement. The working principle is shown with a finite-difference-time-domain (FDTD) CD simulation. Two optical post lithography wafers, including one focus-exposure-matrix (FEM) wafer and one nominal wafer, are inspected for CD, dose and focus analysis. It is demonstrated that dose and focus can be measured independently. A data output method based on global CD uniformity (CDU), inter CDU and intra CDU is proposed to avoid the data volume issue in dense sampling whole wafer inspection.

Line end shortening and iso-dense etch bias improvement by ALD spacer shrink process

Abstract Multiple patterning employing etch shrink extends the scaling of hardmask open CD (HCD) to sub-50nm regime. A plasma-assisted shrink technique is primarily used in the back-end-of-line (BEOL) however it faces major challenges such as the line end shortening (LES) and large critical dimension iso-dense bias (IDB). In order to mitigate these two problems we apply an atomic layer deposition (ALD) spacer shrink process at 10nm metal interconnect layer with sub-20nm minimum half-pitch. As a result we observed 8nm LES improvement in tip-to-tip (T2T) two-dimensional (2D) structures, and 5nm IDB reduction in one-dimensional (1D) structures. These improvements suggest that the ALD spacer shrink can contribute to more precise CD control in multiple patterning.

10nm local interconnect challenge with iso-dense loading and improvement with ALD spacer process

10nm M1 local interconnect is using three-color litho-etch-litho-etch-litho-etch (LELELE) integration to enable technology scaling. This paper discusses the challenges to balance the three-color density in critical standard cell scaling, illustrates the limited process margin resulting from iso-dense loading during dry etch CD shrink, and proposes a novel ALD spacer-shrink process which improves iso-dense CD difference by 50%.

Evaluation of lens heating effect in high transmission NTD processes at the 20nm technology node

The NTD (Negative Tone Developer) process has been embraced as a viable alternative to traditionally, more conventional, positive tone develop processes. Advanced technology nodes have necessitated the adopting of NTD processes to achieve such tight design specifications in critical dimensions. Dark field contact layers are prime candidates for NTD processing due to its high imaging contrast. However, reticles used in NTD processes are highly transparent. The transmission rate of those masks can be over 85%. Consequently, lens heating effects result in a non-trivial impact that can limit NTD usability in a high volume mass production environment. At the same time, Source Mask Optimized (SMO) freeform pupils have become popular. This can also result in untoward lens heating effects which are localized in the lens. This can result in a unique drift behavior with each Zernike throughout the exposing of wafers. In this paper, we present our experience and lessons learned from lens heating with NTD processes. The results of this study indicate that lens heating makes impact on drift behavior of each Zernike during exposure while source pupil shape make an impact on the amplitude of Zernike drift. Existing lens models should be finely tuned to establish the correct compensation for drift. Computational modeling for lens heating can be considered as one of these opportunities. Pattern shapes, such as dense and iso pattern, can have different drift behavior during lens heating.

20nm VIA BEOL patterning challenges

Higher density on 20nm logic chips require tighter pitches to be implemented not only at critical metal layers, but at BEOL critical VIA layers as well. Smaller pitches on critical via are no longer achievable through the conventional positive tone development (PTD) process. Instead, negative tone development (NTD) is considered, evaluated, and integrated as an alternative, along with the double patterning (DP) method. Additionally, preliminary results on NTD+DP patterning challenges, including patterning verification, are presented in this paper.

High order wafer alignment for 20nm node logic process

Advanced thermal annealing processes used for transistor enhancing for the state of the art process nodes induce wafer grid deformations. RTA (Rapid Thermal Anneal) and LSA (Laser Scanning Anneal) processes are a few examples. High Order Wafer Alignment (HOWA) method is an effective wafer alignment strategy for wafers with distorted grid signature especially when wafer-to-wafer grid distortion variations are also present. However, usage of HOWA in high volume production environment requires 1) careful initial determination of optimum polynomial order and alignment sampling to be implemented, and 2) matched tool monitoring and controlling strategies and infrastructures to avoid potential HOWA induced drawbacks (i.e. alignment walking).