Sohan Singh Mehta

Assessment of negative tone development challenges

The objective of this work is to describe the advances in 193nm photoresists using negative tone developer and key challenges associated with 20nm and beyond technology nodes. Unlike positive tone resists which use protected polymer as the etch block, negative tone developer resists must adhere to a substrate with a deprotected polymer matrix; this poses adhesion and bonding challenges for this new patterning technology. This problem can be addressed when these photo resists are coated on anti-reflective coatings with plentiful silicon in them (SiARC), which are specifically tailored for compatibility with the solvent developing resist. We characterized these modified SiARC materials and found improvement in pattern collapse thru-pitches down to 100nm. Fundamental studies were carried out to understand the interactions between the resist materials and the developers. Different types of developers were evaluated and the best candidate was down selected for contact holes and line space applications. The negative tone developer proximity behavior has been investigated through optical proximity correction (OPC) verification. The defectivity through wafer has been driven down from over 1000 adders/wafer to less than 100 adders/wafer by optimizing the develop process. Electric yield test has been conducted and compared between positive tone and negative tone developer strategies. In addition, we have done extensive experimental work to reduce negative tone developer volume per wafer to bring cost of ownership (CoO) to a value that is equal or even lower than that of positive tone CoO.

Integration of an EUV metal layer: a 20/14nm demo

EUV technology has steadily progressed over the years including the introduction of a pre-production NXE:3100 scanner that has enabled EUV process development to advance one step closer to production. We have carried out the integration with 20/14nm metal layer design rules converting double patterning with ArF immersion process to EUV with a single patterning solution utilizing a NXE3100 exposure tool. The exercise through the integration of a mature test chip with an EUV level has allowed us to have early assessment of the process challenges and new workflow required to enable EUV to the mass production stage. Utilizing the NXE3100 in IMEC, we have developed an OPC model and a lithography process to support 20/14nm node EUV wafer integration of a metal layer in conjunction with immersion ArF. This allows early assessment of mix-and-match overlay for EUV to immersion system that is critical for EUV insertion strategy as well as further understanding of the litho process, OPC, and mask defect control specific to EUV single patterning. Through this work we have demonstrated high wafer yields on a 20nm test vehicle utilizing single EUV Metal layer along with additional ArF immersion levels. We were able to successfully demonstrate low mask defectivity and good via chain and open/short electrical yield. This paper summarize the learning cycles from mask defect mitigation and mix machine overlay through post metal CMP wafer integration highlighting the key accomplishments and future challenges.

New fabrication technology for photonic crystal waveguides

We have developed a deep ultraviolet (DUV) lithography technique for fabricating super dense silicon based photonic crystals. Binary mask is used to create nano scale patterns of very high density. Based on the simulation, photonic crystals with both square and triangular lattice of air cylinders are designed and fabricated to work in communication frequency range (λ within 1.3 to 1.55μm) on amorphous silicon. In order to pattern circular hole we designed different kind of polygons on the mask and layout pattern was under sized at constant pitch. Bottom anti reflection coating (BARC) recipe was developed to improve circularity of the pattern and reduce interhole spacing.

Process variation challenges and resolution in the negative-tone develop double patterning for 20nm and below technology node

Immersion based 20nm technology node and below becoming very challenging to chip designers, process and integration due to multiple patterning to integrate one design layer . Negative tone development (NTD) processes have been well accepted by industry experts for enabling technologies 20 nm and below. 193i double patterning is the technology solution for pitch down to 80 nm. This imposes tight control in critical dimension(CD) variation in double patterning where design patterns are decomposed in two different masks such as in litho-etch-litho etch (LELE). CD bimodality has been widely studied in LELE double patterning. A portion of CD tolerance budget is significantly consumed by variations in CD in double patterning. The objective of this work is to study the process variation challenges and resolution in the Negative Tone Develop Process for 20 nm and Below Technology Node. This paper describes the effect of dose slope on CD variation in negative tone develop LELE process. This effect becomes even more challenging with standalone NTD developer process due to q-time driven CD variation. We studied impact of different stacks with combination of binary and attenuated phase shift mask and estimated dose slope contribution individually from stack and mask type. Mask 3D simulation was carried out to understand theoretical aspect. In order to meet the minimum insulator requirement for the worst case on wafer the overlay and critical dimension uniformity (CDU) budget margins have slimmed. Besides the litho process and tool control using enhanced metrology feedback, the variation control has other dependencies too. Color balancing between the two masks in LELE is helpful in countering effects such as iso-dense bias, and pattern shifting. Dummy insertion and the improved decomposition techniques [2] using multiple lower priority constraints can help to a great extent. Innovative color aware routing techniques [3] can also help with achieving more uniform density and color balanced layouts.

Investigation of trench and contact hole shrink mechanism in the negative tone develop process

The objective of this work was to study the trench and contact hole shrink mechanism in negative tone develop resist processes and its manufacturability challenges associated for 20nm technology nodes and beyond. Process delay from post-exposure to develop, or “queue time”, is studied in detail. The impact of time link delay on resolved critical dimension (CD) is fully characterized for patterned resist and etched geometries as a function of various process changes. In this study, we assembled a detailed, theoretical model and performed experimental work to correlated time link delay to acid diffusion within the resist polymer matrix. Acid diffusion is determined using both a modulation transfer function for diffusion and simple approximation based on Fick’s law of diffusion.

Spot size mode converter for efficient coupling to SiN waveguides

To miniaturize optical passive components or to have optical interconnects replace the current copper/low k interconnects for clock distribution, super high index contrast optics are needed because they allow optical waveguides with small bending radius, ie. < 50um. Silicon nitride core on oxide cladding has loss of <0.1dB/180° for 20um bending radius. However, coupling loss from the fiber to SiN waveguides, with 0.7umx0.7um cross section for single mode, is very large, > 20dB. To reduce the coupling loss, our approach is to have a double-core architecture, where fiber is first coupled to fiber matched waveguide, and then coupling from fiber match waveguide to SiN waveguide through a spot size mode converter. We have found the mode converter loss is reduced by 8dB by reducing the tip of the taper from 0.35um to 0.15um. In this paper, we are reported results of tips with less than 0.1um. We also describe the fabrication technology that enables us to make such fine tip with smooth surfaces.

Thick photosensitive polyimide film side wall angle variability and scum improvement for IC packaging stress control

In this paper, we demonstrate photosensitive polyimide (PSPI) profile optimization to effectively reduce stress concentrations and enable PSPI as protection package-induced stress. Through detailed package simulation, we demonstrate ~45% reduction in stress as the sidewall angle (SWA) of PSPI is increased from 45 to 80 degrees in Cu pillar package types. Through modulation of coating and develop multi-step baking temperature and time, as well as dose energy and post litho surface treatments, we demonstrate a method for reliably obtaining PSPI sidewall angle >75 degree. Additionally, we experimentally validate the simulation findings that PSPI sidewall angle impacts chip package interaction (CPI). Finally, we conclude this paper with PSPI material and tool qualification requirements for future technology node based on current challenges.

High-throughput electrical characterization for robust overlay lithography control

Realizing sensitive, high throughput and robust overlay measurement is a challenge in current 14nm and advanced upcoming nodes with transition to 300mm and upcoming 450mm semiconductor manufacturing, where slight deviation in overlay has significant impact on reliability and yield1). Exponentially increasing number of critical masks in multi-patterning lithoetch, litho-etch (LELE) and subsequent LELELE semiconductor processes require even tighter overlay specification2). Here, we discuss limitations of current image- and diffraction- based overlay measurement techniques to meet these stringent processing requirements due to sensitivity, throughput and low contrast3). We demonstrate a new electrical measurement based technique where resistance is measured for a macro with intentional misalignment between two layers. Overlay is quantified by a parabolic fitting model to resistance where minima and inflection points are extracted to characterize overlay control and process window, respectively. Analyses using transmission electron microscopy show good correlation between actual overlay performance and overlay obtained from fitting. Additionally, excellent correlation of overlay from electrical measurements to existing image- and diffraction- based techniques is found. We also discuss challenges of integrating electrical measurement based approach in semiconductor manufacturing from Back End of Line (BEOL) perspective. Our findings open up a new pathway for accessing simultaneous overlay as well as process window and margins from a robust, high throughput and electrical measurement approach.

Investigating deprotection-induced shrinkage and retro-grade sidewalls in NTD resists

Two aspects of NTD resists, deprotection-induced shrinkage, and retrograde sidewalls, are investigated through experimentation and simulation. Simulation predicts that NTD resist profiles should often have retrograde sidewall angles due to the attenuation of light as it propagates down through the resist. Resist shrinkage induced from both the de-protection during PEB and from exposure to electrons during SEM can cause CD and sidewall changes. The interplay between the shrinkage and the retrograde sidewalls is discussed. Deprotection-induced shrinkage is measured by AFM while SEM induced shrinkage is estimated from repeated SEM measurements. SEM images for various features are analyzed and compared to simulation.

Evaluation of lens heating effect in high transmission NTD processes at the 20nm technology node

The NTD (Negative Tone Developer) process has been embraced as a viable alternative to traditionally, more conventional, positive tone develop processes. Advanced technology nodes have necessitated the adopting of NTD processes to achieve such tight design specifications in critical dimensions. Dark field contact layers are prime candidates for NTD processing due to its high imaging contrast. However, reticles used in NTD processes are highly transparent. The transmission rate of those masks can be over 85%. Consequently, lens heating effects result in a non-trivial impact that can limit NTD usability in a high volume mass production environment. At the same time, Source Mask Optimized (SMO) freeform pupils have become popular. This can also result in untoward lens heating effects which are localized in the lens. This can result in a unique drift behavior with each Zernike throughout the exposing of wafers. In this paper, we present our experience and lessons learned from lens heating with NTD processes. The results of this study indicate that lens heating makes impact on drift behavior of each Zernike during exposure while source pupil shape make an impact on the amplitude of Zernike drift. Existing lens models should be finely tuned to establish the correct compensation for drift. Computational modeling for lens heating can be considered as one of these opportunities. Pattern shapes, such as dense and iso pattern, can have different drift behavior during lens heating.