Siavash Fallahi

An 8.5–11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition

An 8.5-11.5Gbps SONET transceiver with a referenceless CDR employing an algorithmic frequency acquisition scheme (without using any training sequence) is designed in a 65nm digital CMOS process. A modified digital quadricorrelator frequency detector (M-DQFD) is incorporated into an LC-based VCO coarse tuning adjustment. The transceiver complies with stringent SONET OC-192 jitter requirements. Within a 400μs acquisition time, the RX achieves a high-frequency jitter tolerance of 0.58UIpp at 10mVpp-diff input sensitivity. The TX serial output exhibits a random jitter (RJ) of 205fs (rms). The transceiver occupies 0.97mm2 and consumes 141mA at 1.0V.

A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS

This paper presents a power- and area-efficient multistandard serial link transceiver designed for backplane application rates of up to 28 Gb/s, such as OIF CEI-25G, CEI-28G, and IEEE 802.3bj 100G-KR4. The receiver features a continuous-time linear equalizer, variable gain amplifier, and a 14-tap decision feedback equalizer, including eight floating taps. The transmitter has a 2:1 multiplexer with a duty cycle distortion corrected half-rate clock and a full-rate source-series terminated driver with a 5-tap feed-forward equalizer. The shared PLL employs a transformer-based LC-VCO that achieves a VCO tuning range of 20G to 29 GHz and 0.23 ps RMS jitter at 28.125 GHz. The transmitter output shows only 50 fs duty-cycle distortion. The transceiver can compensate a 40 dB insertion loss backplane channel (excluding package) at a data rate of 25.78 Gb/s with eight channels running simultaneously. It is fabricated in 28 nm standard CMOS and analog section consumes only 295 mW at 1 V supply with transmitter driver at 1.25 V. Such low power consumption and performance are achieved by combination of advanced 28 nm process, low power and performance driven receiver and transmitter topologies, widely adopted bandwidth extension techniques, built-in analog calibrations and one common PLL with a transformer based VCO for four transceivers.

3.1 A 28Gb/s multi-standard serial-link transceiver for backplane applications in 28nm CMOS

Rapid internet traffic growth has fueled the demand for bandwidth in metro networks and data centers and pushed the serial link data rate into 25Gb/s territory, populated by such electrical interface as OIF CEI-25G, CEI-28G [1], IEEE 802.3bj 100G-KR4. To cope with severe channel impairments at 25Gb/s with up to 30dB loss at Nyquist, a feed-forward equalizer (FFE)/decision feedback equalizer (DFE) based transceiver without power-hungry analog-to-digital converter (ADC) provides robust performance. This work presents a low-power and area-efficient transceiver that employs a 14-tap adaptive DFE at the receiver (RX) and a 5-tap FFE at the transmitter (TX) for multi-standard applications up to 28Gb/s in 28nm CMOS.

A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications

An 8.0 GHz to 12.2 GHz PLL with a capacitor multiplier-based active loop filter is designed in a 28 nm digital CMOS process. A passive loop filter-based version of the PLL is also implemented for comparison. While the PLL area is comparable to that of digital PLLs, the PLL performance is as good as that of an analog PLL that employs a passive loop filter. The capacitor multiplier-based active loop filter PLL has a jitter performance of 198 fs (rms), while its passive loop filter-based counterpart shows a jitter performance of 195 fs (rms). The PLL occupies 0.093 mm2 and consumes 15.5 mA at 1.0V.

11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications

In this paper, an 11.3 Gbps CMOS SONET compliant transceiver designed to work in both RZ and NRZ data formats is presented. Using a configurable high-speed transmit path utilizing an AND gate and a duty cycle adjustment circuit, the transmitter can switch output format between RZ and NRZ. The TX driver exhibits 17 ps rise/fall times, 0.25 psrms RJ, and 2 pspp DJ. In RZ mode, TX output duty cycle can be adjusted within 40-60% range. To improve input sensitivity in both RZ and NRZ reception, the receiver incorporates a limiting amplifier with a distributed threshold adjustment circuit. It achieves 5 mVpp-diff RX input sensitivity with 0.54 UI high-frequency jitter tolerance. An adaptation scheme based on nested linear search is implemented to control the distributed threshold adjustment circuit. While demonstrating the integration of RZ/NRZ functionality into a single-chip solution using 65 nm CMOS technology, the transceiver core occupies 1.36 mm2 and consumes 214 mW.

A 19 mW/lane Serdes transceiver for SFI-5.1 application

A low-power, small-area transceiver PHY that supports SFI-5.1 is fabricated in standard 40 nm CMOS, supporting rates up to 50 Gb/s. The combined active core area of the receiver (RX) and transmitter (TX) occupies only 0.08 mm2 per lane. The RX can handle 0.65 UI (RJ + DJ) plus 0.49 UI additional sinusoidal input jitter, and the TX has only 5.4 ps of ISI. Sixteen lanes plus deskew and clock source channels consume 19 mW of power at 3.125 Gb/s per lane.

An 8.5–11.5Gbps SONET transceiver with referenceless frequency acquisition

An 8.5-11.5-Gbps SONET transceiver with referenceless clock and data recovery (CDR) employing an algorithmic frequency acquisition scheme is presented. Without any training sequence, the frequency acquisition algorithm utilizes a modified digital quadricorrelator frequency detector (M-DQFD) incorporated into an LC-based VCO coarse tuning adjustment. M-DQFD eliminates the dead-zone problem associated with high dispersion and low SNR links. Fabricated in 65-nm CMOS process, the transceiver complies with stringent OC-192 jitter requirements. With a 400- μs acquisition time, the receiver achieves a high-frequency jitter tolerance of 0.58UIpp at 10-mVppd input sensitivity. The transmitter output exhibits a random jitter of 205fsrms. The transceiver occupies 0.97 mm2 and consumes 125 mA at 1.0-V supply voltage.