Sidharth Balasubramanian

Systematic Analysis of Interleaved Digital-to-Analog Converters

A generalized theoretical analysis of interleaved digital-to-analog converters (DACs) is presented to explain the cancellation of image replicas. A new RF-DAC architecture comprising N -parallel DACs and using both clock and hold interleaving structure is proposed. The architecture is analyzed using a general mathematical model that can be extended to other types of interleaved DACs. Additional benefits of the proposed architecture, including bandwidth and resolution enhancements, are investigated. The model is extended to analyze return-to-zero variants of this architecture with a variable hold time period. The effect of different path mismatches is further examined.

Current and Emerging Trends in the Design of Digital-to-Analog Converters

This chapter aims to describe some of the design challenges and emerging trends for high-speed and high-resolution digital-to-analog converters (DACs). We present an overview of the digital-to-analog conversion process and delve into DAC characterization by outlining different sources of error and metrics used to quantify the DAC performance. A summary of current-steering (CS) DAC topologies and circuit limitations is provided, and we details four major considerations in the design space of CS DACs providing a supplemental approach to segmentation. Finally an in-depth survey of current and emerging architectural trends in high-performance DACs is discussed.

A new broadcast format and receiver architecture for radio controlled clocks

A new broadcast format is presented for the atomic-clock time-code signal broadcast by the National Institute of Standards of Technology (NIST) from station WWVB in Fort Collins, Colorado. The new broadcast format, based on BPSK modulation that is added to the existing amplitude-modulation (AM), offers many new features and provides several orders of magnitude of improvement in reception robustness, without impacting existing AM receivers that are based on envelope-detection. Additionally, a digital receiver architecture, amenable to integration in a CMOS system-on-chip (SoC), is proposed, which relies on digital signal processing, thereby eliminating the need for the crystal filter and other passive components found in existing receivers.

Toward Millimeter-Wave DACs: Challenges and Opportunities

As line widths in emerging III-V technologies approaching that of modern CMOS, the conception of high performance mixed signal designs such as digital to analog converters (DACs) in the mm-wave space becomes possible. While addressing the speed limitations, candidate III-Vs (InP, GaAs and GaN) are known to suffer from increased switching power consumption, limited device yield and absolute accuracy. CMOS, on the other hand, has the benefit of low-power digital switching, fine resolution and scalability. Recent attempts in marrying the two technologies have been carried out in the DARPA COSMOS program, by integrating III-V type devices with CMOS circuits, so as to exploit the advantages of low-power digital CMOS and high-speed high-power InP. This paper presents some of the challenges as well as prospects in designing record speed and performance DACs in the COSMOS program while contrasting it to that of deeply-scaled CMOS. A multi-phase parallel DAC architecture is leveraged for ultra-wideband synthesis, to improve noise performance and achieve higher information rates. The architectural bounds between CMOS and InP as well as detailed circuit-level analysis of critical block elements will be highlighted.

Coding-based transceiver for phased array with significant hardware reduction

We proposed a novel reduced hardware receiver architecture with on-site coding. The proposed system offers a substantial reduction in the number of ADCs, and hence, fewer FPGA I/O pins. This results in a significant SWAP-C reduction, making digital beamforming with multiple concurrent beams more practical for large arrays. The proposed system was successfully simulated for two signal paths with Walsh codes and preliminary simulations demonstrated the recovery of the signal with a minor degradation of 0.8 dB in Eb/No. This was compensated for by combining the signals in digital baseband resulting in a 2.2 dB combining gain.

Analytical and Experimental Study of Wide Tuning Range mm-Wave CMOS LC-VCOs

The unprecedented interest in high bandwidth applications in the mm-wave range has set off a wave of research exploring techniques that enable wide tuning range voltage-controlled oscillators (VCOs). Low frequency CMOS LC-VCOs ( <;10 GHz) have been well studied in the literature and several approaches have been developed to optimize their performance. However, there lie several interesting challenges in the mm-wave space, specifically close to the fT/fmax, that motivate the need for analyzing the tuning range and phase noise in mm-wave VCOs. This paper presents a detailed analysis of the ultimate performance bound in simultaneously achieving low phase noise and wide tuning range in CMOS VCOs. The analysis is conducted on a 130 nm CMOS process, and confirmed by measurement results on three VCOs at 26 GHz, 34 GHz and 40 GHz. Finally, the impact of CMOS technology scaling (from 130 nm down to 45 nm), on the achievable performance bounds is analyzed and presented.

Architectural trends in GHz speed DACs

Recent interests from the research community in building digitized transmitters has led to numerous architectural and circuit-level developments in the design of digital-to-analog converters (DACs) in the GHz space. Several challenges exist in terms of interface overhead and process capabilities that fundamentally influence the achievable speed and performance numbers. This paper aims to provide the reader with some of the emerging architectural innovations that address these challenges and aid in the transition of DACs into the GHz regime.

Accuracy and speed limitations in DACs across CMOS process technologies

We present a study of accuracy and timing limitations in current-steering digital-to-analog converters (DACs). Effects of limited output impedance and device mismatches on the DAC performance are discussed and observed for a 10-bit DAC operating at 4 GS/s. These limitations are also studied across 180, 90, and 65 nm CMOS process technologies.

Optical modulators using planar split ring resonators

Split rings have been used very much as resonators and filters at microwave and optical frequencies. This paper discusses the design of a bus-coupled planar split ring resonator (SRR) and develops necessary theory that helps to view it as a potential candidate for the design of optical modulators.