Waleed Khalil

Ultrafast nanoscale metal-semiconductor-metal photodetectors on bulk and low-temperature grown GaAs

Metal‐semiconductor‐metal photodetectors of finger spacing and width as small as 100 nm have been fabricated on bulk and low‐temperature grown GaAs, and tested using a femtosecond pulse laser and high‐speed electro‐optic sampling. The fastest photodetectors have a measured full width at half maximum impulse response and a 3‐dB bandwidth of 0.87 ps and 510 GHz, respectively, for low‐temperature grown GaAs limited by carrier recombination time; and of 1.5 ps and 295 GHz for bulk GaAs, limited by the RC time constant. To our knowledge, they are the fastest detectors of their kinds reported to date.

60-GHz Two-Dimensionally Scanning Array Employing Wideband Planar Switched Beam Network

A two-dimensionally (2-D) scanning array employing a planar switched beam network (SBN) is proposed for 60-GHz high data rate wireless communication. SBNs offer a number of advantages including low cost, multibeam operation, simple direction finding, and minimal power consumption. Unlike existing switched beam arrays operating at 60 GHz, the proposed array scans in both planes. Also, in contrast to 2-D scanning stacks of Butler matrices and Rotman lenses, the proposed SBN is uniplanar and, hence, leads to low-cost manufacturing and integration with 60-GHz radios. The network produces eight 2-D beam states and demonstrates beamforming capability across the entire band of interest (57-64 GHz) with the aid of dummy crossover structures. It is printed on a Rogers Duroid 5880 substrate along with a 2 × 4 patch array. This letter describes the design, operation, and realization of the beamforming array. Simulated and measured performance results are presented to verify the design.

A 1 MHz Bandwidth, 6 GHz 0.18

A 6 GHz Type-I fractional-N PLL with noise-cancelling DAC and discrete-time sample and hold loop-filter is presented. The 1 MHz bandwidth PLL utilizes an inherently linear PFD and noise-cancelling charge-pump DAC circuit to reduce quantization noise by more than 25 dB. The worst case near-integer in-band spur is measured at -61 dBc and the integrated RMS phase error is - 42 dBc. The measured in-band phase noise at 300 kHz offset from the 6.12 GHz carrier is -102 dBc/Hz and out-of-band phase noise at 3 MHz offset is -130 dBc/Hz. The PLL loop settling time for an accuracy of 0.01 ppm and a frequency step of 60 MHz is less than 11 ? s. The synthesizer is fabricated in a 0.18 ?m CMOS technology with 6 metal layers and consumes 26 mA from a 1.8 V power supply.

\mu

Wideband low-noise SigmaDelta fractional-N synthesizers pose several design challenges due to the nonlinear time-varying nature of synthesizer building blocks such as phase frequency detectors (PFDs), charge pump, and frequency dividers. Loop nonlinearities can increase close-in phase noise and enhance spurious tones due to intermodulation of high-frequency quantization noise and tonal content; therefore, an accurate simulation model is critical for successful implementation of loop parameters and bandwidth widening techniques. In this paper a closed-loop nonlinear simulation model for fractional-N synthesizers is presented. Inherent nonuniform sampling of the PFD is modeled through an event-driven dual-iteration-based technique. The proposed technique generates a vector of piecewise linear time-voltage pairs, defining the voltage-controlled oscillator (VCO) control voltage. This method also lends itself to modeling of cyclostationary thermal and flicker noise generated by time-varying charge-pump current pulses. A flexible third-order SigmaDelta modulated RF synthesizer core with integrated loop filter and LC-tank VCO is designed and fabricated in 0.13-mum CMOS process in order to validate the technique experimentally. The proposed modeling technique was able to predict in-band spur power levels with 1.8-dB accuracy, and spur frequency offsets with lower than 400-Hz accuracy with several programmable nonidealities enabled

m CMOS Type-I

Built-in self test techniques for local oscillator phase noise, RF front-end circuits, baseband building blocks and transceiver loop-back are described. CMOS implementation of integrated RF test components, including RF detectors and phase discriminators are introduced. These devices eliminate the need for expensive external test equipment. The presented test strategies can also be used at wafer-level for fault diagnosis, localization and yield estimation. Silicon characterization results verifying most of these techniques are provided.

\Delta \Sigma

Several wireless biomedical transceivers, including medical implants communication systems (MICSs), require ultra-low-power low-complexity frequency synthesizers. This paper presents an all-digital frequency-locked loop (ADFLL)-based frequency synthesizer with a built-in frequency-shift keying modulator for MICS and industrial-scientific-medical band applications. Unlike all-digital phase-locked loops that rely on a power-hungry time to digital converter, the proposed ADFLL employs a high-resolution single-bit ΣΔ frequency discriminator in the feedback path and a noise-cancelling ΣΔ phase-accumulator-based frequency controller in the reference path, achieving fractional resolution with low power consumption. The loop compensation is implemented digitally using an infinite impulse response filter followed by a digital-intensive current-steering DAC driving a ring-oscillator-based voltage-controlled oscillator. The ADFLL achieves 9.5-Hz frequency resolution, spanning the ISM 400-410-MHz band. A worst case near-integer spur of -62 dBc and a phase noise of -83 dBc/Hz at 300-kHz offset are measured. The ADFLL is fabricated on a 0.18-μm CMOS process, occupying a 0.14-mm2 die area, with a quiescent current consumption of 700 μA.

Fractional- N Synthesizer for WiMAX Applications

An on-chip phase-noise-measurement circuit with single-tone measurement sensitivity of -75dBc at 100kHz offset from carrier is presented. The circuit uses a delay-line and mixer frequency discriminator and can operate up to 2GHz input frequency. This module does not rely on a reference clock and, with on-line self calibration, its accuracy is stabilized across gate-delay variations.

Closed-Loop Nonlinear Modeling of Wideband

A generalized theoretical analysis of interleaved digital-to-analog converters (DACs) is presented to explain the cancellation of image replicas. A new RF-DAC architecture comprising N -parallel DACs and using both clock and hold interleaving structure is proposed. The architecture is analyzed using a general mathematical model that can be extended to other types of interleaved DACs. Additional benefits of the proposed architecture, including bandwidth and resolution enhancements, are investigated. The model is extended to analyze return-to-zero variants of this architecture with a variable hold time period. The effect of different path mismatches is further examined.

SigmaDelta

This paper presents a resistor-free temperature compensated CMOS current reference designed in a standard 0.18 um CMOS process. The temperature compensation scheme is achieved by combining a PTC (Positive Temperature Coefficient) current generator circuit with a NTC (Negative Temperature Coefficient) current generator circuit. The proposed design is shown to be less sensitive to process and temperature variations and well suited for integration into other circuits as an accurate and stable current source. Simulation results for the proposed current reference show a temperature coefficient of 170 ppm/°C over a temperature range of 20 °C to 120 °C and an output current variation of 3% over a power supply range of 2 V to 3 V.

Fractional-

An ultra wideband LC voltage-controlled oscillator (LC-VCO) operating in the Ka-band with equally spaced sub-band coarse tuning characteristics is proposed and characterized. A tunable negative capacitance (TNC) circuit technique is used to cancel the fixed capacitance in the LC-tank to extend the tuning range (TR). A digitally-switched varactor coarse tuning structure with an inductance redistribution technique is utilized to reduce VCO gain (KV) and retain uniform spacing between tuning curves. The proposed VCO structure and a baseline VCO are fabricated in a 130 nm CMOS process. Compared to the reference VCO, the proposed VCO achieves a 34% increase in TR with maximum KV of 450 MHz/V. The measured worst-case phase noise is -100.1 dBc/Hz at 1 MHz offset across the TR from 30.5 GHz to 39.6 GHz. The power dissipation of the VCO core is 11 mW from a 1.2 V supply. The TNC-based VCO achieves a FOMT of -189 dBc/Hz, which is the highest reported at the Ka-band.