Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Gregory L. Creech is active.

Publication


Featured researches published by Gregory L. Creech.


IEEE Transactions on Microwave Theory and Techniques | 1997

Artificial neural networks for fast and accurate EM-CAD of microwave circuits

Gregory L. Creech; Bradley J. Paul; Christopher D. Lesniak; Thomas J. Jenkins; Mark C. Calcatera

A novel approach for achieving fast and accurate computer-aided design (CAD) of microwave circuits is described. The proposed approach enhances the ability to utilize electromagnetic (EM) analysis techniques in an interactive CAD environment through the application of neurocomputing technology. Specifically, a multilayer perceptron neural network (MLPNN) is implemented to model monolithic microwave integrated circuit (MMIC) passive elements using the elements physical parameters. The strength of this approach is that only a minimum number of EM simulations of these passive elements are required to capture critical input-output relationships. The technique used to describe the data set required for model development is based on a statistical design of experiment (DoE) approach. Data generated from EM simulations are used to train the MLPNN which, once trained, is capable of modeling passive elements not included in the training set. The results presented indicate that the MLPNN can predict the s-parameters of these passive elements to nearly the same degree of accuracy as that afforded by EM simulation. The correlations between the MLPNN-computed and EM-simulated results are greater than 0.98 for each modeled parameter.


IEEE Transactions on Circuits and Systems Ii-express Briefs | 2011

Systematic Analysis of Interleaved Digital-to-Analog Converters

Sidharth Balasubramanian; Gregory L. Creech; James Wilson; Samantha Yoder; Jamin J. McCue; Marian Verhelst; Waleed Khalil

A generalized theoretical analysis of interleaved digital-to-analog converters (DACs) is presented to explain the cancellation of image replicas. A new RF-DAC architecture comprising N -parallel DACs and using both clock and hold interleaving structure is proposed. The architecture is analyzed using a general mathematical model that can be extended to other types of interleaved DACs. Additional benefits of the proposed architecture, including bandwidth and resolution enhancements, are investigated. The model is extended to analyze return-to-zero variants of this architecture with a variable hold time period. The effect of different path mismatches is further examined.


IEEE Design & Test of Computers | 2012

Mixed-Signal SoCs With In Situ Self-Healing Circuitry

Christopher Maxey; Gregory L. Creech; Sanjay Raman; Jay Rockway; Kari Groves; Tony Quach; Len Orlando; Aji Mattamana

This article discusses the goals and recent achievements of the HEALICs program. The programs aim is to enhance wireless systems with sensors, actuators, and mixed-signal control loops in order to improve their performance yield.


international microwave symposium | 1996

Artificial neural networks for accurate microwave CAD applications

Gregory L. Creech; Bradley J. Paul; Christopher D. Lesniak; T. Jenkins; R. Lee; Mark C. Calcatera

A unique approach for applying neurocomputing technology for accurate CAD of microwave circuits is described. In our proposed method, a multilayer perceptron neural network (MLPNN) is trained to predict the scattering parameters of MMIC passive elements based on the elements physical dimensions. The s-parameters were obtained by performing a full-wave electromagnetic (EM) analysis of these elements. An X-band MLPNN spiral inductor model is developed. The MLPNN computed s-parameter values are in excellent agreement with those obtained from EM simulations with correlations greater than 0.99 for all modelled parameters.


radio frequency integrated circuits symposium | 2013

A −189 dBc/Hz FOM T wide tuning range Ka-band VCO using tunable negative capacitance and inductance redistribution

Qiyang Wu; Salma Elabd; Tony Quach; Aji Mattamana; Steve R. Dooley; Jamin J. McCue; Pompei L. Orlando; Gregory L. Creech; Waleed Khalil

An ultra wideband LC voltage-controlled oscillator (LC-VCO) operating in the Ka-band with equally spaced sub-band coarse tuning characteristics is proposed and characterized. A tunable negative capacitance (TNC) circuit technique is used to cancel the fixed capacitance in the LC-tank to extend the tuning range (TR). A digitally-switched varactor coarse tuning structure with an inductance redistribution technique is utilized to reduce VCO gain (KV) and retain uniform spacing between tuning curves. The proposed VCO structure and a baseline VCO are fabricated in a 130 nm CMOS process. Compared to the reference VCO, the proposed VCO achieves a 34% increase in TR with maximum KV of 450 MHz/V. The measured worst-case phase noise is -100.1 dBc/Hz at 1 MHz offset across the TR from 30.5 GHz to 39.6 GHz. The power dissipation of the VCO core is 11 mW from a 1.2 V supply. The TNC-based VCO achieves a FOMT of -189 dBc/Hz, which is the highest reported at the Ka-band.


IEEE Transactions on Circuits and Systems Ii-express Briefs | 2013

Frequency Tuning Range Extension in LC-VCOs Using Negative-Capacitance Circuits

Qiyang Wu; Tony Quach; Aji Mattamana; Salma Elabd; Pompei L. Orlando; Steven R. Dooley; Jamin J. McCue; Gregory L. Creech; Waleed Khalil

We present an experimentally validated capacitance cancellation structure to increase the tuning range (TR) of LC voltage-controlled oscillators (VCOs) with minimal phase noise or power impact. The cancellation is based on an ultrawideband differential active negative-capacitance (NC) circuit. An NC scheme suitable for bottom-biased VCOs is analyzed and combined with a CMOS VCO to cancel the fixed capacitance in the LC tank. The NC structure is further modified to be tunable, enabling additional expansion of the VCO TR. By manipulating the quality factor (Q) of the NC tuning varactor pair, a prototype VCO achieves a maximum TR of 27% in a 130-nm technology, while dissipating 13 mA from a 0.9-V supply. The TR is the highest reported at Q-band, covering from 34.5 GHz to 45.4 GHz. Compared to the reference VCO without an NC circuit, the TR is increased by 38%. The measured worst case phase noise is -95 dBc/Hz at 1-MHz offset, and the FOMT is -184.9 dBc/Hz.


ieee gallium arsenide integrated circuit symposium | 1998

Accurate and efficient small-signal modeling of active devices using artificial neural networks

P.M. Watson; Mark H. Weatherspoon; Lawrence Dunleavy; Gregory L. Creech

Artificial neural networks (ANNs) are presented for the accurate and efficient small-signal modeling of active devices. Models are developed using measured data and are valid over ranges of parameters such as frequency, bias, and ambient temperature. Once generated, these ANN models are inserted into commercial microwave circuit simulators where they can be used for computer-aided design (CAD) and optimization of microwave/MM-wave circuits. Also, the developed ANN models can give physical insight into device behavior and scaling properties when used in conjunction with an equivalent circuit approach. An advantage of the ANN modeling approach is that it provides substantial data storage reduction over previously used modeling techniques without loss of accuracy. With increased model accuracy, the potential of first-pass design success may be realized, resulting in cost savings and decreased time-to-market for new products.


international symposium on circuits and systems | 1995

Feedforward neural networks for estimating IC parametric yield and device characterization

Gregory L. Creech; Jacek M. Zurada; Peter Aronhime

A unique and accurate approach for modeling semiconductor device characteristics and estimating IC parametric yield is described. Multilayer perceptron neural networks (MLPNN) are trained using error back propagation to model DC device characteristics measured at the final fabrication stage. Measurements of material and/or device characteristics taken at earlier fabrication stages are used to develop neural network models of the final DC parameters. A very good agreement has been found between the actual measurements and the MLPNN modeled parameters, and the resulting yield estimations are in excellent agreement with the actual yield.


compound semiconductor integrated circuit symposium | 2012

Design of Wide Tuning-Range mm-Wave VCOs Using Negative Capacitance

Qiyang Wu; Tony Quach; Aji Mattamana; Salma Elabd; Steven R. Dooley; Jamin J. McCue; Pompei L. Orlando; Gregory L. Creech; Waleed Khalil

Negative capacitance (NC) circuits of single-ended and differential topologies are presented, analyzed and characterized. The novel NC designs extend the bandwidth of conventional NC circuits while maintaining low power consumption. To compare the performance of the designs, a figure of merit (FOM) is proposed. A power and area efficient NC scheme employing a 130 nm CMOS technology is applied to a mm-wave LC Voltage Controlled Oscillator (LC-VCO) for demonstration. The VCO tuning range is extended by employing the NC circuit to cancel the parasitic capacitance of the LC-tank; resulting in a 35% tuning range increase as compared to the reference LC-VCO circuit. The NC-based LC-VCO achieved a 27% tuning range in the Q-Band, which is the highest reported. Measured results compare closely to the theoretical analysis of the LC-VCO operating from 34.5-45.4 GHz.


compound semiconductor integrated circuit symposium | 2005

X-band low noise amplifier using SiGe BiCMOS technology

Vipul J. Patel; H.S. Axtell; C. Cerny; Gregory L. Creech; R. Drangmeister; M.A. Gouker; T.L. James; A.G. Mattamana; I.O. Mbuko; R.A. Neidhard; E.B. Nykiel; P.L. Orlando; D.L. Selke; J.M. Wiedemann; T.K. Quach

An X-band (8-12 GHz) low-noise amplifier (LNA) for receiver systems is presented. The microwave monolithic integrated circuit (MMIC) with no external matching components has been demonstrated using a 0.18 /spl mu/m silicon germanium (SiGe) bipolar CMOS (BiCMOS) technology. The amplifier employs a two-stage topology to achieve low noise figure and high linearity across 8-12 GHz. At 10 GHz the LNA yielded a gain of 24.2 dB, a noise figure of 1.68 dB, and a third-order intercept point of 17.5 dBm. The power dissipation of the circuit is 33.6 mW using a 1.8 V supply voltage. To the best of our knowledge, the circuit achieves the lowest noise figure for a wide bandwidth LNA realized in a SiGe technology.

Collaboration


Dive into the Gregory L. Creech's collaboration.

Top Co-Authors

Avatar

Tony Quach

Air Force Research Laboratory

View shared research outputs
Top Co-Authors

Avatar

Aji Mattamana

Air Force Research Laboratory

View shared research outputs
Top Co-Authors

Avatar

Pompei L. Orlando

Air Force Research Laboratory

View shared research outputs
Top Co-Authors

Avatar
Top Co-Authors

Avatar

Vipul J. Patel

Air Force Research Laboratory

View shared research outputs
Top Co-Authors

Avatar

H.S. Axtell

Air Force Research Laboratory

View shared research outputs
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar

Qiyang Wu

Ohio State University

View shared research outputs
Top Co-Authors

Avatar

R. Drangmeister

Massachusetts Institute of Technology

View shared research outputs
Researchain Logo
Decentralizing Knowledge