Vipul J. Patel

InP HBT/Si CMOS-Based 13-b 1.33-Gsps Digital-to-Analog Converter With > 70-dB SFDR

Gigahertz-rate Digital-to-Analog Converters (DACs) have become readily available from several commercial vendors but have been unable to achieve >;70 dB spurious-free dynamic range (SFDR) performance over a wide bandwidth (≥500MHz). This paper presents the results of a unique, heterogeneously-integrated (InP HBT with 0.18um silicon CMOS), 13-bit 1.33Gsps DAC that achieves >;70dB SFDR across a 500MHz bandwidth in the second Nyquist zone (750MHz to 1250MHz).

X-band low noise amplifier using SiGe BiCMOS technology

An X-band (8-12 GHz) low-noise amplifier (LNA) for receiver systems is presented. The microwave monolithic integrated circuit (MMIC) with no external matching components has been demonstrated using a 0.18 /spl mu/m silicon germanium (SiGe) bipolar CMOS (BiCMOS) technology. The amplifier employs a two-stage topology to achieve low noise figure and high linearity across 8-12 GHz. At 10 GHz the LNA yielded a gain of 24.2 dB, a noise figure of 1.68 dB, and a third-order intercept point of 17.5 dBm. The power dissipation of the circuit is 33.6 mW using a 1.8 V supply voltage. To the best of our knowledge, the circuit achieves the lowest noise figure for a wide bandwidth LNA realized in a SiGe technology.

InP HBT/Si CMOS-Based 13-Bit 1.33Gsps Digital-to-Analog Converter with >70 dB SFDR

Abstract - Gigahertz-rate Digital-to-Analog Converters (DACs) have become readily available from several commercial vendors but have been unable to achieve >70 dB spurious-free dynamic range (SFDR) performance over a wide bandwidth (≥500MHz). This paper presents the results of a unique, heterogeneously-integrated (InP HBT with 0.18um silicon CMOS), 13-bit 1.33Gsps DAC that achieves >70dB SFDR across a 500MHz bandwidth in the second Nyquist zone (750MHz to 1250MHz).

An indium phosphide X-band class-E power MMIC with 40% bandwidth

A broadband, high efficiency, X-band power amplifier is presented in this paper. The single-stage amplifier is based on indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. In order to obtain high efficiency operation, a switch mode, class-E amplifier topology was selected. Special attention has been paid to providing the required fundamental matching conditions, as well as appropriate harmonic terminations, over the frequency band of interest. As a result, the amplifier obtained a bandwidth of 40%, with 45-60% PAE, 19-21.5dBm Pout, and 9-11.5dB large-signal gain at X-band. To the best of our knowledge, this circuit demonstrates the widest bandwidth for a class-E amplifier at X-band.

A Time-Interleaved Multimode

A multi-mode delta-sigma (ΔΣ) RF digital-to-analog converter (RF-DAC) is proposed for direct digital-to-RF synthesis. Unlike embedded-mixer ΔΣ RF-DACs which require analog I/Q combining and precise alignment of the local oscillator (LO) and data clock, the proposed circuit is fully digital with only one clock frequency (fS). This architecture eliminates the need for a widely-tuned LO by reconfiguring the ΔΣ modulator (DSM) for a variety of output frequencies, thus making it suitable for software-defined radio. Both a band-pass (BP) and high-pass (HP) DSM are used to synthesize signals at fS/4, fS/2, or 3fS/4. Interleaving is used to reject the first DAC image, doubling the usable bandwidth of the HP DSM while reducing reconstruction filter requirements. The proposed RF-DAC is implemented in 130 nm SiGe BiCMOS. With an fS of 2 GHz, the 0.18 mm2 RF-DAC core consumes 55 mW with output powers of -4.5 dBm, -7.5 dBm, and -13.8 dBm at 0.5 GHz, 1 GHz, and 1.5 GHz, respectively. For the HP DSM, a signal-to-image rejection ratio (SIRR) of 72 dB, an SNR of 54.5 dB over a 50 MHz bandwidth, and an in-band SFDR of 58.5 dB are demonstrated.A multimode delta-sigma (ΔΣ) RF digital-to-analog converter (RF-DAC) is proposed for direct digital-to-RF synthesis. The proposed circuit uses a single clock frequency (f8) and provides a ΔΣ modulator (DSM) that operates in bandpass (BP) and highpass (HP) modes to synthesize signals around f8/4, f8/2, or 3f8/4. The on-chip 14 bit second-order DSM implements an array of 1 bit pipelined subtract functions to generate 3 bit f8 rate RF-DAC input data. Analog interleaving via a second 3 bit DAC is used to reject the first DAC image, simultaneously doubling the usable bandwidth of the HP DSM and increasing the SNR. Calibration circuits are added to the DAC to compensate for amplitude and timing variations. The proposed RF-DAC is implemented in 130 nm SiGe BiCMOS with an area of 0.563 mm2. Measurements at f8 = 2 GHz yield an output power of -0.6 dBm with 76.2 dB signal-to-image-rejection ratio (SIRR), 76.2 dB SFDR over a 100 MHz bandwidth, -80 dBc IM3, -67.2 dB WCDMA ACLR, and -66.4 dBc LTE ACLR. Changing f8 to 3 GHz allows frequencies of 2.25 GHz to be generated with output power of -16.6 dBm, 65.2 dB SFDR, -62 dBc IM3, -59.3 dB WCDMA ACLR, and -59.2 dBc LTE ACLR.

\Delta\Sigma

This chapter aims to describe some of the design challenges and emerging trends for high-speed and high-resolution digital-to-analog converters (DACs). We present an overview of the digital-to-analog conversion process and delve into DAC characterization by outlining different sources of error and metrics used to quantify the DAC performance. A summary of current-steering (CS) DAC topologies and circuit limitations is provided, and we details four major considerations in the design space of CS DACs providing a supplemental approach to segmentation. Finally an in-depth survey of current and emerging architectural trends in high-performance DACs is discussed.

RF-DAC for Direct Digital-to-RF Synthesis

This paper presents two integrated non-reflective bandpass filters. The filters are implemented in a silicon germanium (SiGe) BiCMOS technology and fully depleted silicon on insulator (FDSOI) CMOS technology. The purpose of these circuits is to explore the feasibility of passive filter applications on silicon substrates while maintaining low insertion loss and 50 Ohm impedance matching. The SiGe-based filter achieved 3.3-4.2 dB insertion loss across 3.5-4.5 GHz with input return loss better than -10 dB from 1-10 GHz. The FDSOI filter simulation yielded an insertion loss of 4.5 dB across the design frequency of 3.7-4.3 GHz

Current and Emerging Trends in the Design of Digital-to-Analog Converters

This paper reports a demonstration of X-band receiver RF front-end components and the integrated chipset implemented in 0.18 mum silicon germanium (SiGe) technology. The system architecture consists of a single down conversion from X-band at the input to S-band at the intermediate frequency (IF) output. The microwave monolithic integrated circuit (MMIC) includes an X-band low noise amplifier, lead-lag splitter, balanced amplifiers, double balanced mixer, absorptive filter, and an IF amplifier. The integrated chip achieved greater than 30 dB of gain and less than 6 dB of noise figure.

RF filters in SiGe BiCMOS technology and fully depleted silicon-on-insulator CMOS technology

Digital-to-analog converters (DACs) are pervasive, critical components for radios and various signal processing systems. Therefore, a myriad of research efforts, covering architectural, circuit, and technological aspects have been made towards improving the performance of DACs. However, the quest to achieve stringent dynamic linearity requirements (>70 dBc SFDR ) over many gigahertz of bandwidth presents grand challenges to designers and high-yield manufacturers. In light of these challenges, various calibration and compensation techniques have evolved over the past two decades to overcome design and process technology variations and limitations.

X-Band Receiver Front-End Chip in Silicon Germanium Technology

Wide-band digital drivers are indispensable for SMPAs (Switched Mode Power Amplifiers) in PWM (Pulse Width Modulation) and PPM (Pulse Position Modulation) applications. This paper presents the design of a wideband RF pre-amplifying buffer, innovated for very low dropout and low power complementary operation in heterojunction technologies affording only depletion type devices. A simple, passive bias level shifting technique is also incorporated to facilitate interfacing the digital modulator in silicon substrate with the PA in III-V wafer. In order to experimentally validate the concepts, the proposed driver is employed for driving an S-band single-ended class-E PA as well as for its differential version, modified to switch over S and C bands, in 130 nm GaAs pHEMT technology. The output powers of the differential amplifier are combined using on-chip transformer balun. Test results of both chips demonstrate that the implemented drivers consume less than 4% of the overall PA efficiencies, wherein the buffer responds linearly to the wideband input pulses when tested alone.