Sidney P. Huey

Technological breakthrough in pad life improvement and its impact on CMP CoC

Many IC fabs have expressed a great deal of interest in CMP pad life improvement with the expectation that improved pad performance will reduce process variability and improve CMP cost-of-consumables (CoC). Critical parameters that impact grooved-pad life and that can reduce pad life variability have been identified through designed experiments performed on a multiple head/platen CMP tool. The most important parameters effecting pad life are groove quality and groove size. New technologies have been developed to control these critical parameters in conjunction with extensive process optimization. Lathing technology (in tools and processes) plays a critical role in achieving high groove quality and desirable groove size. In many extended wafer runs and several accelerated pad wear runs, pad life was more than doubled by optimizing these critical parameters on polyurethane-based grooved-pads. Low defect counts of <20 at 0.2 /spl mu/m, low within wafer non-uniformity (WIWNU) of 4% with a 5 mm edge exclusion, and a stable removal rate of >2750 Ang./min. were achieved for thermal oxide CMP in the extended runs. The new pads double pad life when used with optimized processes, and achieve planarity comparable to conventional pads. Significant pad life improvement was attributed mainly to the implementation of larger and more consistent grooving, and optimized pad conditioning and polishing processes for the CMP tool. In general, the pad cost contributes approximately one third of the total CMP CoC. In this case study, average CMP pad life was found to be 250 wafers/pad with a variance of 100 to 400 wafers/pad. Pad CoC significantly increases for pad lives <350 wafers/pad. The pad CoC at 350 wafers/pad is half of that at 225 wafers/pad. Based on several extended runs, new pads coupled with an optimized polish process demonstrated the feasibility of more than 500 wafers/pad. At this longer pad life, the potential to reduce CoC is even greater.

A Novel Retaining Ring in Advanced Polishing Head Design for Significantly Improved CMP Performance

This paper reports a technological advancement in developing and implementing a novel retaining ring of advanced edge performance (AEP ring) for an advanced polishing head design. The AEP ring has been successfully used for significantly improved CMP performance in different CMP applications: oxide (PMD and ILD), shallow trench isolation (STI), polysilicon, metal (W and Cu), silicon-on-insulator (SOI), and silicon CMP. Robust processes have been developed using AEP ring along with many hardware upgrades for each application with extended runs to meet requirements of advanced IC device fabrication.