Erich Klink

Modeling, simulation, and measurement of mid-frequency simultaneous switching noise in computer systems

Complementary metal-oxide-semiconductor (CMOS) microprocessors operating in the hundreds of megahertz create significant current deltas due to the variation in switching activity front clock cycle to clock cycle. In addition to the high-frequency voltage variations more commonly discussed, a lower frequency noise component is also produced that lasts from 50-200 ns which we refer to as mid-frequency noise. In this paper, we discuss the design of IBMs CMOS S/390 computer for control of mid-frequency noise. This machine has a 10-way multiprocessor on a 127 mm by 127 mm multichip module (MCM) on a FR4 board. The chips on the MCM cause a current step of tens of Amps in a few cycles that can be sustained for many cycles. The power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits. The design of the system power distribution and modeling and verification of mid-frequency noise in this system is presented.

Evolution of organic chip packaging technology for high speed applications

The high dense interconnect (HDI) organic chip packaging technology has made rapid development advancements in the last few years. Due to the dense wiring structures in the build up layers and the recently introduced fine line core with micro vias, high signal input/output (I/O) applications and dense chip area array footprints can be supported. These technology improvements support specific new dense chip applications. In this paper the electrical characteristics and the evolution of this packaging technology is described. The electrical description is especially focussed on material characteristics and the signal integrity including cross talk. In addition the impact on high speed data transmission and the performance differences between single-chip module (SCM) and multichip modules (MCM) are discussed. Also the power integrity is described on the basis of the results of a mid frequency power noise analysis.

Comparison of time- and frequency domain measurement results for product related card and MCM transmission lines up to 65 GHz

Transmission line models and material parameters are extracted from time and frequency domain measurements for product related low loss card and ceramic MCM test line structures up to 65GHz. All measured results are compared to results as obtained from field calculations showing the advantages and limitations of the different methods on product driven test vehicles.

Organic Chip Packaging Technology For High Speed Processor Applications

The high dense interconnect (HDI) organic chip packaging technology has made rapid development advancements in the last few years. Due to the high dense wiring structures in the build up layers and newly also in the laminated core, high signal I/O applications and dense chip area array footprints can be supported. In the present paper the electrical characteristics of the HDI organic chip packaging technology are described with regard to signal and power integrity. In addition different applications for single-chip and multi-chip modules are discussed

Signal propagation over perforated reference planes

Voids on reference planes are commonly seen in organic chip packages and printed circuit boards. In this paper, the effects of these voids on the signal integrity of a high-density data bus will be studied. A generic FCPBGA chip package is used to illustrate the signal integrity concerns and perform sensitivity analysis on the key mechanisms including void size, adjacent plane interactions, and adjacent signal line interactions. The results show that proper design can mitigate the signal integrity impact of reference plane voids.

Power distribution analysis for IBM eServer system integration optimization

Server system design is strongly influenced by power delivery aspects. Multiple requirements and limitations must be taken into consideration. This requires an appropriate DC analysis workflow. This contribution outlines a DC strategy used for IBM eServer design. The strategy is divided into two parts, PrePD and PostPD. PrePD type of analysis is used for system high-level design and optimization including parts selection, number of board layers, module sizing and placement on board, interface pin pattern optimization for both module to board and board to backplane. PostPD analysis is used for first level packaging design optimization and verification. The combination of PrePD and PostPD analysis serves as an efficient and useful tool, shown by the examples of various applications, for server power delivery system design.

Practical Considerations in the Modeling and Characterization of Printed-Circuit Board Wiring

The importance of increased accuracy in modeling and characterization of printed-circuit board wiring is highlighted through practical examples. Recommendations are given regarding model causality, bandwidth, measurement methodology improvement for both production-level and off-line monitoring of impedance, roughness, and dielectric loss and their significance for system design, performance, delivery, and cost is discussed

Novel organic chip packaging technology and impacts on high speed interfaces

The high dense interconnect (HDI) organic chip packaging technology has made rapid development advancements in the last few years. Due to the dense wiring structures in the build up layers and newly also in the laminated core, high signal I/O applications and dense chip area array footprints can be supported. These technology improvements allow specific applications. In this paper the electrical characteristics of the HDI organic chip packaging technology are described with regard to signal and power noise. In addition the impact on high speed data transmission and the performance differences between single-chip module (SCM) and multi-chip modules (MCM) are discussed.

Impact of Broken High Frequency Signal Return Path on Signal Integrity

Special test vehicles with and without broken high frequency signal return paths were built in order to measure their impact on signal integrity. Design guidelines for the transition between different packaging levels are derived and discussed

Sensitivity analysis of generic on-chip /spl Delta/I-noise simulation methodology

Power integrity, i.e. providing a stable voltage supply under the condition of rapidly changing current transients, gets increasing attention in the design of electronic packaging. Part of this discussion is the on-chip /spl Delta/I-noise. Various simulation methodologies, e.g. RAPiD, are known for simulation. Characteristic for these simulations is the very time consuming task of collecting and processing the complex input data, in order to optimise the required effort a sensitivity analysis for high-frequency on-chip /spl Delta/I-noise simulation has been carried out. This paper describes the results of this sensitivity analysis. A generic description of the on-chip /spl Delta/I-noise simulation methodology is shown. In particular the required input data is described. The sensitivity analysis quantifies the impact of each simulation parameter on the simulation results. The nominal value of each input parameter has been varied in a range from 0.5x to 2.0x compared to a nominal case. The maximum HF /spl Delta/I-noise is measured and plotted versus the respective input parameter deviation. The input parameters are categorized in high, medium and low impact parameters. This analysis results in guidelines which design parameters most efficiently reduce HF-noise and/or which input parameter need to be accurate in order to obtain accurate simulation results.