Simon J. Mahon

LNA Design Based on an Extracted Single Gate Finger Model

A GaAs low-noise amplifier (LNA) is designed with first-time success using a technique for HEMT modelling which divides the device into intrinsic gate fingers embedded in an analysable metal structure. The gate finger is characterised by de-embedding metallisation from a standard test structure. The device is then re-built, with any geometry or layout that the foundry allows, and modelled by electromagnetic (EM) analysis. This allows techniques such as asymmetric inductive source feedback in an LNA to be modelled without prior fabrication of custom test structures. The 7-13 GHz, self-biased LNA has state-of-the-art noise figure (NF) of 1.25 dB at mid-band, gain of 20.5 ± 0.1 dB with 10 dB input and output matches, 10 dBm P1dB, 14 dBm Psat and 22 dBm OIP3. Excellent agreement is achieved with simulation. In a 3x3 QFN package the measured NF is 1.36 dB and the gain is 20 dB. The first-time design success achieved here validates the modelling and parameter extraction technique.

Robust Extraction of Access Elements for Broadband Small-signal FET Models

A small-signal transistor model extraction technique is proposed. It partitions access and intrinsic elements with a more accurate network for the intrinsic section. This resolves problems of nonphysical parameters and inconsistencies across bias. The technique uses low gate and zero drain bias measurements to directly determine an access network. There is no need to apply electrical stress to the device during measurement. The procedure is deterministic.

Impact of Bias and Device Structure on Gate Junction Temperature in AlGaN/GaN-on-Si HEMTs

The thermal impact of device bias-state and structures (such as source connected field plates, gate-pitch, back-vias, and number of gate fingers) in AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) are measured using gate metal resistance thermometry (GMRT). The technique characterizes the thermal response of device gate metallization to determine the gate-epilayer junction temperature (Tj), which is directly influenced by the channel heat source due to its close proximity. It is found that low gate leakage levels in GaN HEMTs make them favorable candidates for GMRT. Bias-dependent self-heating, independent of power dissipation, is observed in the devices. Therefore, Tj of different device configurations are compared at constant bias state, as well as constant power density (3.75 W/mm) to improve accuracy. Tj reduction is observed at high drain bias due to the migration of the channel heat source toward the gate field plate edge. This provides independent experimental validation for a reported electrothermal model [7]. A 3-D thermal finite element method model is presented, which simulates measured Tj rise to within ~6% across a range of device configurations and operating conditions. This is ultimately made possible upon implementation of a thermal boundary resistance layer and extraction of its temperature response using GMRT data.

Study of Gate Junction Temperature in GaAs pHEMTs Using Gate Metal Resistance Thermometry

Gate junction temperature is presented as the crucial parameter for modeling thermal degradation in GaAs device reliability studies, and sufficient for modeling the impact of temperature on device terminal characteristics. Gate metal resistance thermometry (GMRT) is applied to a GaAs pseudomorphic high-electron mobility transistor to measure its gate junction temperature. It is found that gate leakage current due to impact ionization can interfere with dc GMRT measurements. To the best of our knowledge, for the first time it is demonstrated that this can be largely avoided by instead applying an ac version of GMRT. However, the dynamic resistance of the gate leakage current path can interfere with ac GMRT. Measurements and thermal finite element method simulations of devices at constant power dissipation conclude that the bias dependence of the channel heat source profile affects the gate junction temperature. A parameter extraction technique is presented and used in device lifetime calculations to demonstrate MTTF variations of more than an order of magnitude (despite fixed power) due to bias-dependent self-heating.

A scalable linear model for FETs

A small-signal model of the intrinsic region of a microwave FET that considers four capacitance terms is examined. Four reactive terms in the model are required to describe four imaginary Y -parameter terms. The addition of a fourth capacitance rather than a channel resistance or delay term enables extraction of dispersion-free parameters, better consistency with a large-signal model and better scaling properties. An important aspect of the model topology is clear separation of resistive and reactive elements so that transconductance and output conductance correspond to real parts of the Y -parameters. It is shown that this has an impact on the scaling of noise models that are formulated in terms of these resistive parameters.

35 dBm, 35 GHz power amplifier MMICs using 6-inch GaAs pHEMT commercial technology

A 3.5 watt, 35 GHz power amplifier MMIC has been developed. The amplifier exhibits high performance at low processing cost, through the use of a commercially available 6-inch, 0.15-μm pHEMT process with 100 μm thick substrate. The single-ended four stage amplifier MMIC has 22 dB of gain at 35 GHz, 3.5 watts saturated output power (35.5 dBm), and power added efficiency of more than 25%, within a chip size of 12.75 mm2. In terms of power density, this is 740 mW/mm, which is to the authors’ knowledge the best reported for fully matched GaAs pHEMT MMICs on 100-μm substrates at millimetre-wave frequencies.

Compact K-band Watt-level GaAs PHEMT Power Amplifier MMIC with integrated ESD protection

The performance of a compact K-band power amplifier MMIC fabricated in standard 6-inch 0.15-mum GaAs power PHEMT technology is reported. The circuit features on-chip ESD protection including input short-circuit stub, dual capacitors at RF ports and high-current diode arrays on each gate pad. Occupying less than 3 mm2, this 3-stage power amplifier achieves a linear gain of more than 20-dB over the 17 to 24 GHz frequency range with 6-dB noise figure. It also delivers a CW output power of more than 29-and 30-dBm, in the 17-20 GHz band, at 5- and 6-V respectively. Preliminary ESD characterization shows the circuit withstands 180-V in human body model test (tester limit), and 100-V machine model (equivalent to at least 500-V HBM), without DC or RF performance degradation. Finally, performance in standard 24-lead plastic QFN package (4times4 mm2) is presented: the device exhibits more than 17.5-dB linear gain over 17-24 GHz, with P-.1dB greater than 28-dBm in the 17.7-19.7 GHz radio range

A family of 1, 2 and 4-watt power amplifier MMICs for cost effective VSAT ground terminals

A complete family of cost effective power amplifier MMICs for Ka-band VSAT ground terminals has been developed. Taking advantage of a 6-inch, 0.15/spl mu/m pHEMT process on 100-/spl mu/m thick substrate, the amplifiers exhibit high performance at the lower processing cost: the single-ended, 3-stage amplifier MMIC has more than 27-dB gain at 30GHz and 1-watt saturated output power within a chip size of less than 3.9mm/sup 2/. Two versions of 2-watt power amplifiers, differing in bandwidth, have small signal gain of 24 and 21dB between 28 and 32GHz with excellent additional characteristics (36% PAE and 41-dBm OIP/sub 3/); their chip sizes are 9.5 and 7.4mm/sup 2/. Finally, a balanced power amplifier achieves 4watts from 28 to 30GHz, with a power added efficiency of more than 31% and 43-dBm OIP/sub 3/, in a chip area of 14mm/sup 2/. In term of power and gain density per chip area, these results are among the best reported for GaAs pHEMT on 100-/spl mu/m substrates.

Full ETSI E-Band Doubler, Quadrupler and 24 dBm Power Amplifier

A GaAs pHEMT frequency doubler, a quadrupler and a power amplifier for E-band applications have been demonstrated to achieve useful output power and power added efficiency (PAE) over a wide bandwidth. The doubler and quadrupler circuits include medium power amplifiers to increase their gain and output power. The doubler has a measured output power greater than 15 dBm over the entire 15 GHz bandwidth of the European Telecommunications Standards Institute (ETSI) E-band specification. The quadrupler has similar output power over the ETSI E bands with a maximum output power of 19.2 dBm. The power amplifier has a maximum measured output power of 24.2 dBm (265 mW) and exceeds 23 dBm (200 mW) over the ETSI E bands. This amplifier has a measured small signal gain of 15 dB and the input and output return losses exceed 15 dB. Its measured PAE is above 8% across the ETSI E bands. This is the highest saturated output power (Psat) and PAE for a power amplifier spanning the full 71 to 86 GHz span of the ETSI E bands for any semiconductor system. Good agreement is demonstrated between measurement and simulation.

Packaged, Integrated 32 to 40 GHz Millimeter-Wave Up-Converter

A 4 × 4 mm QFN overmoulded packaged up-converter has been developed for the 38 GHz point-to-point radio band. The MMIC contains LO-doubler-buffer amplifier, image-reject balanced mixer and RF amplifier with linear gain control and consumes 1.5 watts DC. The up-converter has 7 dB conversion gain, 15 dB image rejection, 15 dB of gain control, 20 dBm IIP3 and 50 dB LO-to-RF isolation in the mixer. Performance is similar in the 32 GHz band. The up-converter represents the state of the art in performance and cost.