Jabra Tarazi

LNA Design Based on an Extracted Single Gate Finger Model

A GaAs low-noise amplifier (LNA) is designed with first-time success using a technique for HEMT modelling which divides the device into intrinsic gate fingers embedded in an analysable metal structure. The gate finger is characterised by de-embedding metallisation from a standard test structure. The device is then re-built, with any geometry or layout that the foundry allows, and modelled by electromagnetic (EM) analysis. This allows techniques such as asymmetric inductive source feedback in an LNA to be modelled without prior fabrication of custom test structures. The 7-13 GHz, self-biased LNA has state-of-the-art noise figure (NF) of 1.25 dB at mid-band, gain of 20.5 ± 0.1 dB with 10 dB input and output matches, 10 dBm P1dB, 14 dBm Psat and 22 dBm OIP3. Excellent agreement is achieved with simulation. In a 3x3 QFN package the measured NF is 1.36 dB and the gain is 20 dB. The first-time design success achieved here validates the modelling and parameter extraction technique.

A scalable linear model for FETs

A small-signal model of the intrinsic region of a microwave FET that considers four capacitance terms is examined. Four reactive terms in the model are required to describe four imaginary Y -parameter terms. The addition of a fourth capacitance rather than a channel resistance or delay term enables extraction of dispersion-free parameters, better consistency with a large-signal model and better scaling properties. An important aspect of the model topology is clear separation of resistive and reactive elements so that transconductance and output conductance correspond to real parts of the Y -parameters. It is shown that this has an impact on the scaling of noise models that are formulated in terms of these resistive parameters.

Full ETSI E-Band Doubler, Quadrupler and 24 dBm Power Amplifier

A GaAs pHEMT frequency doubler, a quadrupler and a power amplifier for E-band applications have been demonstrated to achieve useful output power and power added efficiency (PAE) over a wide bandwidth. The doubler and quadrupler circuits include medium power amplifiers to increase their gain and output power. The doubler has a measured output power greater than 15 dBm over the entire 15 GHz bandwidth of the European Telecommunications Standards Institute (ETSI) E-band specification. The quadrupler has similar output power over the ETSI E bands with a maximum output power of 19.2 dBm. The power amplifier has a maximum measured output power of 24.2 dBm (265 mW) and exceeds 23 dBm (200 mW) over the ETSI E bands. This amplifier has a measured small signal gain of 15 dB and the input and output return losses exceed 15 dB. Its measured PAE is above 8% across the ETSI E bands. This is the highest saturated output power (Psat) and PAE for a power amplifier spanning the full 71 to 86 GHz span of the ETSI E bands for any semiconductor system. Good agreement is demonstrated between measurement and simulation.

Steady state and transient thermal analyses of GaAs pHEMT devices

GaAs pHEMT thermal reliability test structures are introduced which incorporate on-wafer heating using Thin Film Resistors (TFR) and a DC gate metal temperature measurement method. Results from 3D Finite Element Method (FEM) thermal simulations are compared with measurements and used to investigate the frequency response of device self-heating. Comparisons are made with existing thermal models. The influence of individual device structures on the thermal characteristics of an entire device is investigated and the epitaxial layers are seen to have a large impact on overall performance. Bias dependent self-heating, independent of thermal dissipation is observed and attributed to confinement of the thermal source as the drain voltage is increased.

AlGaN/GaN HEMT nonlinear model fitting including a trap model

A procedure for the extraction of a trap model is applied to an AlGaN/GaN-on-SiC HEMT. The trap model is then used in the extraction of a nonlinear device model. The resulting model accurately relates dc I-V with nonlinear behaviour which is crucial for accurately predicting the load-pull measurements. This modeling procedure can be integrated into a modelling/design flow enabling accurate prediction of device and circuit performance.

Scalable HEMT model for small signal operations

The aim of this work is to develop a scalable small signal HEMT model. We propose a general intrinsic model “unit cell” to build larger transistor devices according to our need and model the metal according to individual geometry using a lumped element network. The challenge we address is extraction of this network from measurement. The parameters of the intrinsic part of the transistor have been extracted from different size of transistors and scaling rule applied to the unit cell. We used MathCAD worksheet to de-embed the TriQuint transistor parameters. Multiple cells are used to build larger devices and we showed that coupling between cells with lumped element affects the S-parameter responses. The interconnection with lumped elements was varied according to the need to fit with larger device responses.

Compact W-Band PA MMICs in Commercially Available 0.1-µm GaAs PHEMT Process

The technology, design aspects and performance of a family of three compact W-band power amplifier MMICs are presented. The circuits are fabricated in a commercially available 0.1-μm GaAs PHEMT technology. Thanks to efficient design approaches, the 3.5-mm2 power amplifier demonstrates a measured linear gain of more than 12 dB, and a saturated output power Psat of +24.5 dBm (280 mW) across the 80-100 GHz band. The driver and medium power amplifiers deliver at 92-96 GHz more than +20.5 dBm (>100 mW) and +23 dBm (200 mW), in chip sizes of less than 0.97 mm2 (0.25 mm2 for the core amplifier) and 1.95 mm2 respectively. These power densities and measured performance at W-band compare favorably to other GaAs MMICs, and more advanced solutions using InP HBTs or GaN HEMTs reported in the literature. Furthermore, the presented design considerations can be applied to reduce manufacturing cost in other circuits and technologies.

0.1-µm GaAs PHEMT W-band low noise amplifier MMIC using coplanar waveguide technology

This paper presents the performance of a first pass design W-band low noise amplifier MMIC, based on coplanar waveguide (CPW) technology, and utilising 100-nm gate-length GaAs pseudomorphic power HEMTs. With a chip size of less than 1.4 mm2, this two-stage LNA achieves an average small signal gain of 12 dB between 80 and 100 GHz. The measured noise figure averages 5 dB up to 94 GHz. To the author knowledge, this performance is one of the very few reported for W-band LNAs fabricated in commercially available foundry process. It is also comparable to the best results reported with more advanced InP or Metamorphic HEMT low noise technologies.

Thermal modelling of multifinger GaAs/GaN FETs using SPICE

A simple thermal model is presented to estimate the junction temperature in multi-finger GaAs and GaN high electron mobility transistors (HEMTs). The model is implemented in SPICE by treating heat flow as analogous to the flow of electric current. The model enables a comprehensive study of different layout possibilities for devices. Results from 3D Finite Element Model (FEM) simulation and from Gate Metal Resistance Thermometry (GMRT) are compared with the model.

Extraction of a trapping model over an extended bias range for GaN and GaAs HEMTs

A simple procedure for extracting parameters of a bias-dependent trap model for GaN and GaAs is presented. The extraction is achieved based on a mapping of the steady-state trap-centre potential for a representative range of the bias voltages. The circuit model of trapping is verified in the process. The time constant for emission is also extracted. It is demonstrated that the model is able to predict device response and time constants in both capture and emission states. Bias-dependence of trapping and associated time constants is successfully modeled.