Simone Borri

Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution

This paper presents an analysis of dynamic faults in core-cell of SRAM memories. These faults are the consequence of resistive-open defects that appear more frequently in VDSM technologies. In particular, the study concentrates on those defects that generate dynamic Read Destructive Faults, dRDFs. In this paper, we demonstrate that read or write operations on a cell involve a stress on the other cells of the same word line. This stress, called Read Equivalent Stress (RES), has the same effect than a read operation. On this basis, we propose to modify the well known March C-, which does not detect dRDFs, into a new version able to detect them. This is obtained by changing its addressing order with the purpose of producing the maximal number of RES. This modification does not change the complexity of the algorithm and its capability to detect the former target faults.

Resistive-open defects in embedded-SRAM core cells: analysis and march test solution

In this paper we present an exhaustive analysis of resistive-open defect in core-cell of SRAM memories. These defects that appear more frequently in VDSM technologies induce a modification of the timing within the memory (delay faults). Among the faults induce by such resistive-open defects there are static and dynamic read destructive fault (RDF), deceptive read destructive fault (DRDF), incorrect read fault (IRF) and transition fault (TF). Each of them requires specific test conditions and different kind of March tests are needed to cover all these faults (TF, RDF, DRDF and IRF). In this paper, we show that a unique March test solution can ensure the complete coverage of all the faults induced by the resistive-open defects in the SRAM core-cells. This solution simplifies considerably the problem of delay fault testing in this part of SRAM memories.

Defect-oriented dynamic fault models for embedded-SRAMs

This paper presents the results of resistive fault insertion in the core-cell array and in the address decoder of the Infineon 0.13 /spl mu/m embedded-SRAM family. Resistive opens defects were the primary target of this study because of their growing importance in VDSM technologies. Electrical simulations have been performed to evaluate the effects of resistive opens in terms of functional faults detected and verify the presence of timing-dependent faults. Read disturb, deceptive read disturb and dynamic read disturb faults have been reproduced and accurately characterized. The dependence of the fault detection on memory operating conditions, injected resistance value and clock speed have been investigated and the importance of speed testing for dynamic fault models is emphasized. Finally resistive address decoder open faults (ADOF) have been simulated and the conditions for maximum fault detection are discussed as well as the resulting implications for memory test.

March iC-: an improved version of March C- for ADOFs detection

This paper presents a new March test solution for detection of ADOFs (Address Decoder Open Faults), and resistive-ADOFs that are the consequence of resistive-open defects in address decoders of SRAM memories. In this study, we briefly analyze the test conditions and the March test requirements for these particular faults and we introduce some modifications to the well known March C- making it able to detect ADOFs and resistive-ADOFs, without increasing its complexity and its ability to detect the former target faults. The reformulation of March C-, called March iC-, is essentially based on introducing a particular address sequence and a particular read/write data sequence. The proposed March iC- extends the ability of March-based test solutions in detecting dynamic faults in SRAM memories.

Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories

This paper presents an analysis of dynamic faults in core-cell of SRAM memories. These faults may appear as the consequence of resistive-open defects that appear more and more frequently in VDSM technologies. In particular, the study concentrates on those defects that generate dynamic Read Destructive Faults, dRDFs. In this paper, we demonstrate that read or write operations on a cell involve a stress on the other cells of the same word line. This stress, called Read Equivalent Stress (RES), has the same effect than a read operation. On this basis, we propose to modify the well known March C-, which does not detect dRDFs, into a new version able to detect them. This is obtained by changing its addressing order with the purpose of producing the maximal number of RES. This modification does not change the complexity of the algorithm and its capability to detect the former target faults.

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test

This paper presents the results of resistive-open defect insertion in different locations of Infineon 0.13 μm embedded-SRAM with the main purpose of verifying the presence of dynamic faults. This study is based on the injection of resistive defects as their presence in VDSM technologies is more and more frequent. Electrical simulations have been performed to evaluate the effects of those defects in terms of detected functional faults. Read destructive, deceptive read destructive and dynamic read destructive faults have been reproduced and accurately characterized. The dependence of the fault detection has been put in relation with memory operating conditions, resistance value and clock cycle, and the importance of at speed testing for dynamic fault models has been pointed out. Finally resistive Address Decoder Open Faults (ADOF) have been simulated and the conditions that maximize the fault detection have been discussed as well as the resulting implications for memory test.

ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions

This paper presents a comparative analysis of ADOFs (Address Decoder Open Faults) and resistive-ADOFs in embedded-SRAMs. Such faults are the primary target of this study because they are hard-to-detect faults. These faults are caused by some particular defects which may appear in the parallel transistor network of the logic gates in the address decoders. With this study, we show that the test conditions required for ADOFs testing (sensitization and observation) are also useful for resistive-ADOFs detection, but more stringent timing requirements are needed. In the last part of the paper, we propose a study on the conditions to detect ADOFs with March tests. Moreover, we propose new March elements, which are effective for ADOF testing, and which can be added to existing March tests.

A silicon-based yield gain evaluation methodology for embedded-SRAMs with different redundancy scenarios

Yield improvement is an essential issue for modem high-volume manufacturing CMOS processes. Process yield is particularly low for area-critical designs, such as embedded memories. The use of redundancy structures which replace faulty memory locations with good ones, has a direct impact on the final chip yield. This paper describes an experimental methodology employed to evaluate the yield gain associated with different redundancy approaches and shows how this method can be applied to determine the optimal redundancy configuration which maximizes the number of good dies per wafer, depending on the embedded memory requirements of a specific product.