Sofie Mertens

Cost-effective cleaning and high-quality thin gate oxides

Some recent findings in the area of wafer cleaning and thin oxide properties are presented in this paper. Results are shown for a practical implementation of a simplified cleaning concept that combines excellent performance in terms of metal and particle removal with low chemical and DI-water consumption. The effect of organic contamination on ultrathin gate-oxide integrity is illustrated, and the feasibility of using ozonated DI water as an organic removal step is discussed. Metal outplating from HF and HF/HCI solutions is investigated. Also, the final rinsing step is critically evaluated. It is demonstrated that Si surface roughness without the presence of metal contaminants does not degrade gate-oxide integrity. Finally, some critical remarks on the reliability measurements for ultrathin gate oxides are given; it is shown that erroneous conclusions can be drawn from constant-current charge-to-breakdown measurements.

The VO2 interface, the metal-insulator transition tunnel junction, and the metal-insulator transition switch On-Off resistance

Transition metal compounds showing a metal-insulator transition (MIT) show complex behavior due to strongly correlated electron effects and offer attractive properties for nano-electronics applications, which cannot be obtained with regular semiconductors. MIT based nano-electronics, however, remains unproven, and MIT devices are poorly understood. We point out and single out one of the major hurdles preventing MIT-electronics: obtaining a high Off resistance and high On-Off resistance ratio in an MIT switch. We show a path toward an MIT switch fulfilling strict Off and On resistance criteria by: (1) Obtaining understanding of the VO2-interface, a protoypical MIT material interface. (2) Introducing a MIT tunnel junction concept to tune switch resistances. In this junction, the metal or insulating phase of the MIT material controls how much current flows through. Adapting the junctions parameters allows tuning the MIT switchs Off and On resistance. (3) Providing proof of principle of the junction and its...

Silicide yield improvement with NiPtSi formation by laser anneal for advanced low power platform CMOS technology

A novel silicide formation technique using milli-second anneal is reported for the first time, delivering superior silicide film morphology that translates electrically into significant yield improvement over a conventional soak anneal, without any degradation of transistor performances. In addition, we demonstrate how this new technique enables the integration of thin silicides required for further junction scaling, and demonstrate up to 6nm gate length reduction and more than 1 decade junction leakage imporvement.

BEOL compatible high tunnel magneto resistance perpendicular magnetic tunnel junctions using a sacrificial Mg layer as CoFeB free layer cap

Perpendicularly magnetized MgO-based tunnel junctions are envisaged for future generation spin-torque transfer magnetoresistive random access memory devices. Achieving a high tunnel magneto resistance and preserving it together with the perpendicular magnetic anisotropy during BEOL CMOS processing are key challenges to overcome. The industry standard technique to deposit the CoFeB/MgO/CoFeB tunnel junctions is physical vapor deposition. In this letter, we report on the use of an ultrathin Mg layer as free layer cap to protect the CoFeB free layer from sputtering induced damage during the Ta electrode deposition. When Ta is deposited directly on CoFeB, a fraction of the surface of the CoFeB is sputtered even when Ta is deposited with very low deposition rates. When depositing a thin Mg layer prior to Ta deposition, the sputtering of CoFeB is prevented. The ultra-thin Mg layer is sputtered completely after Ta deposition. Therefore, the Mg acts as a sacrificial layer that protects the CoFeB from sputter-indu...

Gatestacks for scalable high-performance FinFETs

Excellent performance (995 muA/mum at Ioff=94 n A/mum and Vdd=lV) and short channel effect control are achieved for tall, narrow FinFETs without mobility enhancement. Near-ideal fin/gate profiles are achieved with standard 193 nm immersion lithography and dry etch. PVD TiN electrodes on Hf SiO dielectrics are shown to give improved NMOS performance over PEALD TiN whilst poorer conformality, for both dielectric and gate electrode, does not appear to impact scalability or performance. Excellent PMOS performance is achieved for both PEALD and PVD TiN. A new model for threshold voltage VT variability is shown to explain this dependence upon fin width and gate length.

Co/Ni based p-MTJ stack for sub-20nm high density stand alone and high performance embedded memory application

Excellent tunnel magneto resistance (TMR) values of 143% at resistance-area products (RA) of 4.7 Ωμm2 from 11nm thin Co/Ni based perpendicular magnetic tunnel junctions (p-MTJ) was achieved. Engineered wetting layer (WL), seed layer (SL) and the introduction of newly designed inner synthetic anti-ferromagnetic (iSAF) pinned layer in combination with ultra-smooth bottom electrode (roughness 0.5 Å) was yielded to vertically scaled 11nm thick Co/Ni p-MTJ stack with excellent magnetic properties. The introduction of iSAF layer demonstrates for the 1st time the free layer offset field controllability (<; 100 Oe) of the spin-transfer-torque (STT) magnetic random access memory (MRAM) device down to 12 nm in diameter.

Impact of gate oxide nitridation process on 1/f noise in 0.18 μm CMOS

Abstract The aim of this paper is to study the impact of the nitridation techniques on the 1/f noise performances of dual gate 0.18 μm CMOS transistors. Nitrogen is often introduced to prevent boron penetration in ultrathin oxides especially when BF2 is used for the PMOS junction implantation, but as a result the MOS transistor exhibits higher 1/f noise because of the increased fixed trap density. We show how the nitridation process can be improved in terms of 1/f noise characteristics, in a fully integrated technology. Projections of the 1/f noise behaviour for different technologies are also shown, to emphasise how the 1/f noise becomes an issue when other downscaling properties are considered for analog/RF CMOS applications.

Scalability of plasma enhanced atomic layer deposited ruthenium films for interconnect applications

Ru thin films were deposited by plasma enhanced atomic layer deposition using MethylCyclopentadienylPyrrolylRuthenium (MeCpPy)Ru and N2/NH3 plasma. The growth characteristics have been studied on titanium nitride or tantalum nitride substrates of various thicknesses. On SiO2, a large incubation period has been observed, which can be resolved by the use of a metal nitride layer of ∼ 0.8 nm. The growth characteristics of Ru layers deposited on ultra-thin metal nitride layers are similar to those on thick metal nitride substrates despite the fact that the metal nitride layers are not fully closed. Scaled Ru/metal nitride stacks were deposited in narrow lines down to 25 nm width. Thinning of the metal nitride does not impact the conformality of the Ru layer in the narrow lines. For the thinnest lines the Ru deposited on the side wall showed a more granular structure when compared to the bottom of the trench, which is attributed to the plasma directionality during the deposition process.

Thin Co/Ni-based bottom pinned spin-transfer torque magnetic random access memory stacks with high annealing tolerance

Spin-transfer torque magnetic random access memory (STT-MRAM) is considered as a replacement for next generation embedded and stand-alone memory applications. One of the main challenges in the STT-MRAM stack development is the compatibility of the stack with CMOS process flows in which thermal budgets up to 400 °C are applied. In this letter, we report on a perpendicularly magnetized MgO-based tunnel junction (p-MTJ) on a thin Co/Ni perpendicular synthetic antiferromagnetic layer with high annealing tolerance. Tunnel magneto resistance (TMR) loss after annealing occurs when the reference layer loses its perpendicular magnetic anisotropy due to reduction of the CoFeB/MgO interfacial anisotropy. A stable Co/Ni based p-MTJ stack with TMR values of 130% at resistance-area products of 9 Ω μm2 after 400 °C anneal is achieved via moment control of the Co/Ta/CoFeB reference layer. Thinning of the CoFeB polarizing layer down to 0.8 nm is the key enabler to achieve 400 °C compatibility with limited TMR loss. Thinning the Co below 0.6 nm leads to a loss of the antiferromagnetic interlayer exchange coupling strength through Ru. Insight into the thickness and moment engineering of the reference layer is displayed to obtain the best magnetic properties and high thermal stability for thin Co/Ni SAF-based STT-MRAM stacks.

Switching mechanism in two-terminal vanadium dioxide devices

Two-terminal thin film VO2 devices show an abrupt decrease of resistance when the current or voltage applied exceeds a threshold value. This phenomenon is often described as a field-induced metal-insulator transition. We fabricate nano-scale devices with different electrode separations down to 100 nm and study how the dc switching voltage and current depend on device size and temperature. Our observations are consistent with a Joule heating mechanism governing the switching. Pulsed measurements show a switching time to the high resistance state of the order of one hundred nanoseconds, consistent with heat dissipation time. In spite of the Joule heating mechanism which is expected to induce device degradation, devices can be switched for more than 10(10) cycles making VO2 a promising material for nanoelectronic applications.