Marc Schaekers

Plasma-enhanced chemical vapour deposition growth of Si nanowires with low melting point metal catalysts: an effective alternative to Au-mediated growth

Au nanoparticles are efficient catalysts for the vapour?solid?liquid (VLS) growth of semiconductor nanowires, but Au poses fundamental reliability concerns for applications in Si semiconductor technology. In this work we show that the choice of catalysts for Si nanowire growth can be broadened when the need for catalytic precursor dissociation is eliminated through the use of plasma enhancement. However, in this regime the incubation time for the activation of VLS growth must be minimized to avoid burying the catalyst particles underneath an amorphous Si layer. We show that the combined use of plasma enhancement and the use of a catalyst such as In, already in a liquid form at the growth temperature, is a powerful method for obtaining Si nanowire growth with high yield. Si nanowires grown by this method are monocrystalline and generally oriented in the direction.

Germanium surface passivation and atomic layer deposition of high-k dielectrics?a tutorial review on Ge-based MOS capacitors

Due to its high intrinsic mobility, germanium (Ge) is a promising candidate as a channel material (offering a mobility gain of approximately??2 for electrons and??4 for holes when compared to conventional Si channels). However, many issues still need to be addressed before Ge can be implemented in high-performance field-effect-transistor (FET) devices. One of the key issues is to provide a high-quality interfacial layer, which does not lead to substantial drive current degradation in both low equivalent oxide thickness and short channel regime. In recent years, a wide range of materials and processes have been investigated to obtain proper interfacial properties, including different methods for Ge surface passivation, various high-k dielectrics and metal gate materials and deposition methods, and different post-deposition annealing treatments. It is observed that each process step can significantly affect the overall metal?oxide?semiconductor (MOS)-FET device performance. In this review, we describe and compare combinations of the most commonly used Ge surface passivation methods (e.g. epi-Si passivation, surface oxidation and/or nitridation, and S-passivation) with various high-k dielectrics. In particular, plasma-based processes for surface passivation in combination with plasma-enhanced atomic layer deposition for high-k depositions are shown to result in high-quality MOS structures. To further improve properties, the gate stack can be annealed after deposition. The effects of annealing temperature and ambient on the electrical properties of the MOS structure are also discussed.

Semiconductor-metal transition in thin VO2 films grown by ozone based atomic layer deposition

Vanadium dioxide (VO2) has the interesting feature that it undergoes a reversible semiconductor-metal transition (SMT) when the temperature is varied near its transition temperature at 68°C.1 The variation in optical constants makes VO2 useful as a coating material for e.g. thermochromic windows,2 while the associated change in resistivity could be interesting for applications in microelectronics, e.g. for resistive switches and memories.3 Due to aggressive scaling and increasing integration complexity, atomic layer deposition (ALD) is gaining importance for depositing oxides in microelectronics. However, attempts to deposit VO2 by ALD result in most cases in the undesirable V2O5. In the present work, we demonstrate the growth of VO2 by using Tetrakis[EthylMethylAmino]Vanadium and ozone in an ALD process at only 150°C. XPS reveals a 4+ oxidation state for the vanadium, related to VO2. Films deposited on SiO2 are amorphous, but during a thermal treatment in inert gas at 450°C VO2(R) is formed as the first and only crystalline phase. The semiconductor-metal transition has been observed both with in-situ X-ray diffraction and resistivity measurements. Near a temperature of 67°C, the crystal structure changes from VO2(M1) below the transition temperature to VO2(R) above with a hysteresis of 12°C. Correlated to this phase change, the resistivity varies over more than 2 orders of magnitude.

Cost-effective cleaning and high-quality thin gate oxides

Some recent findings in the area of wafer cleaning and thin oxide properties are presented in this paper. Results are shown for a practical implementation of a simplified cleaning concept that combines excellent performance in terms of metal and particle removal with low chemical and DI-water consumption. The effect of organic contamination on ultrathin gate-oxide integrity is illustrated, and the feasibility of using ozonated DI water as an organic removal step is discussed. Metal outplating from HF and HF/HCI solutions is investigated. Also, the final rinsing step is critically evaluated. It is demonstrated that Si surface roughness without the presence of metal contaminants does not degrade gate-oxide integrity. Finally, some critical remarks on the reliability measurements for ultrathin gate oxides are given; it is shown that erroneous conclusions can be drawn from constant-current charge-to-breakdown measurements.

Implementing TiO2 as gate dielectric for Ge-channel complementary metal-oxide-semiconductor devices by using HfO2/GeO2 interlayer

The electrical properties of plasma-enhanced atomic-layer-deposited (PE-ALD) TiO2 as gate dielectric were investigated for germanium-channel complementary metal-oxide-semiconductor capacitors by using ultrathin in situ HfO2/GeO2 interlayers. TiO2 grown by PE-ALD exhibited a k value of 50±5. An equivalent oxide thickness of 0.9 nm was obtained for the TiO2(3 nm)/HfO2(1.2 nm)/GeO2(0.7 nm)/Ge capacitor with very low leakage current density of 2×10−7 A/cm2 at VFB±1 V. Capacitance-voltage hysteresis was below 30 mV for the TiO2/HfO2/GeO2/Ge capacitors. Relatively low minimum density of interface states, Dit ∼5×1011 eV−1 cm−2 was obtained, suggesting the potential of HfO2/GeO2 passivation layer for the application of TiO2 as gate dielectric for both p- and n-type Ge channels.

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

Strained Ge p-channel FinFETs on Strain Relaxed SiGe are integrated for the first time on high density 45nm Fin pitch using a replacement channel approach on Si substrate. In comparison to our previous work on isolated sGe FinFETs [1], 14/16nm technology node compatible modules such as replacement metal gate and germanide-free local interconnect were implemented. The ION/IOFF benchmark shows the high density strained Ge p-FinFETs in this work outperform the best published isolated strained Ge on SiGe devices.

Multiring Circular Transmission Line Model for Ultralow Contact Resistivity Extraction

Accurate determination of contact resistivities (P_c) below 1 × 10^-8 Ω · cm² is challenging. Among the frequently applied transmission line models (TLMs), circular TLM (CTLM) has a simple process flow, while refined TLM (RTLM) has a high Pc accuracy at the expense of a more complex fabrication. In this letter, we will present a novel model-multiring CTLM (MR-CTLM), which combines the advantages of a simple process and a high <i>Pc</i> extraction resolution. We fabricated ultralow<i>-Pc</i> Ti/n-Si contacts and demonstrated the capability of MR-CTLM to extract the P_c as low as 6.2 × 10^-9 Ω · cm² with high precision.

Ultrathin GeOxNy interlayer formed by in situ NH3 plasma pretreatment for passivation of germanium metal-oxide-semiconductor devices

In situ NH3 plasma surface-nitridation treatments at 250 °C on both p- and n-type Ge(100) wafers were investigated. An ultrathin high quality GeOxNy interlayer was formed and exhibited dielectric breakdown for electric fields greater than 15 MV/cm. Well behaved capacitance-voltage characteristics were obtained for the complementary metal-oxide-semiconductor capacitors (CMOSCAPs) with HfO2(3 nm)/GeOxNy(1 nm) gate stacks. Gate leakage current density was below 5×10−7 A/cm2 at VFB±1 V for both MOSCAPs with an equivalent oxide thickness of 1.1 nm. Promising electrical properties of the CMOSCAPs indicate effective passivation of the Ge interface with GeOxNy interlayer formed by in situ NH3 plasma treatment.

Impact of gate oxide nitridation process on 1/f noise in 0.18 μm CMOS

Abstract The aim of this paper is to study the impact of the nitridation techniques on the 1/f noise performances of dual gate 0.18 μm CMOS transistors. Nitrogen is often introduced to prevent boron penetration in ultrathin oxides especially when BF2 is used for the PMOS junction implantation, but as a result the MOS transistor exhibits higher 1/f noise because of the increased fixed trap density. We show how the nitridation process can be improved in terms of 1/f noise characteristics, in a fully integrated technology. Projections of the 1/f noise behaviour for different technologies are also shown, to emphasise how the 1/f noise becomes an issue when other downscaling properties are considered for analog/RF CMOS applications.

A Simplified Method for (Circular) Transmission Line Model Simulation and Ultralow Contact Resistivity Extraction

The metal resistance in the transmission line model (TLM) structures creates a serious obstacle to determine precisely the intrinsic contact resistivity. To tackle this problem, we propose a new model, the lump model, to evaluate the metal resistance influence in both TLM and circular TLM (CTLM) test structures. In this letter, we demonstrate the high simplicity, great robustness, and flexibility of the lump model. The previous reported contact resistivity values extracted with CTLM are usually above 1 χ 10-7Ω · cm2 because the metal resistance impact is commonly neglected. This is the first time that the role of the metal in CTLM is appropriately analyzed. Low contact resistivity, 3.6χ10-8Ω · cm2, of standard NiSi/n-Si contact has been extracted and this shows the high sensitivity of this method.