Xiaoping Shi

The VO2 interface, the metal-insulator transition tunnel junction, and the metal-insulator transition switch On-Off resistance

Transition metal compounds showing a metal-insulator transition (MIT) show complex behavior due to strongly correlated electron effects and offer attractive properties for nano-electronics applications, which cannot be obtained with regular semiconductors. MIT based nano-electronics, however, remains unproven, and MIT devices are poorly understood. We point out and single out one of the major hurdles preventing MIT-electronics: obtaining a high Off resistance and high On-Off resistance ratio in an MIT switch. We show a path toward an MIT switch fulfilling strict Off and On resistance criteria by: (1) Obtaining understanding of the VO2-interface, a protoypical MIT material interface. (2) Introducing a MIT tunnel junction concept to tune switch resistances. In this junction, the metal or insulating phase of the MIT material controls how much current flows through. Adapting the junctions parameters allows tuning the MIT switchs Off and On resistance. (3) Providing proof of principle of the junction and its...

Atomic Layer Deposition of Gd-Doped HfO2 Thin Films

Gd x Hf 1-x O y thin films were deposited by atomic layer deposition (ALD) using tris(isopropyl-cyclopentadienyl) gadolinium [Gd( i PrCp) 3 ] and HfCl 4 in combination with H 2 0 as an oxidizer. Growth curves showed a nearly ideal ALD behavior. The growth per individual Gd( i PrCp) 3 /H 2 O or HfCl 4 /H 2 O cycle was 0.55 A, independent of the Gd/(Gd + Hf) composition x in the studied range. This indicates that the amount of HfO 2 deposited during a HfCl 4 /H 2 O cycle was essentially identical to the amount of Gd 2 O 3 deposited during a Gd( i PrCp) 3 /H 2 O cycle, assuming identical atomic densities of the films independent of composition. The crystallization of Gd x Hf 1-x O y , with Gd/(Gd + Hf) contents x between 7 and 30% was studied. Films with x ≳ 10% crystallized into a cubic/tetragonal HfO 2 -like phase during spike or laser annealing up to 1300°C, demonstrating that the cubic/tetragonal phase is thermally stable in this temperature range. A maximum dielectric constant of K ~ 36 was found for a Gd/(Gd + Hf) concentration of x ~ 11%.

Lateral and vertical scaling of a QSA HBT for a 0.13/spl mu/m 200GHz SiGe:C BiCMOS technology

A 200 GHz F/sub t/ SiGe:C HBT has been integrated into a 0.13 /spl mu/m BiCMOS technology. A previous generation low complexity quasi self-aligned architecture (QSA) is scaled down both in a lateral and vertical way. Lateral sizing is obtained by using present-day step and scan tools. Vertical sizing is achieved by reducing the thermal budget of the active module and by an aggressive scaling of the SiGe:C base epitaxial layer. A deep trench module, featuring a thick oxide liner, has been developed. Excellent DC parameters and peak Ft/Fmax values of 200/160 GHz are demonstrated. The CMOS device characteristics remain unchanged by applying low thermal budget processing in the bipolar module.

CMP-less integration of fully Ni-silicided metal gates in FinFETs by simultaneous silicidation of the source, drain, and the gate using a novel dual hard mask approach

We demonstrate a novel CMP-less dual hard mask scheme for the integration of fully silicided gates in FinFETs by simultaneous silicidation of the gate, source and the drain. V/sub T/ of 0.18V and -0.2V are demonstrated for 50nm gate length NFET and PFET respectively. Competitive I/sub on/-I/sub off/ of 960uA/um-140nA/um for NFET and 620uA/um-100nA/um for PFET were obtained at V/sub D/=l .3V for an EOT of 1.8nm.

Low V t Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases

This paper reports a novel approach to implement low V_t Ni-FUSI bulk CMOS by using a dysprosium oxide (DyO) cap layer on both HfSiON and SiON host dielectrics. We show for the first time that an ultra-thin DyO cap layer (5 Aring) can lower the NiSi FUSI nFET V_t by 300 mV/500 mV on HfSiON/SiON (resulting in a V_t,lin of 0.25 V/0.18 V respectively), w/o compromising the T_inv (<1 Aring variation), gate leakage, mobility or reliability. We observed that the DyO cap on SiON can convert into a DySiON silicate with similar electrical properties as HfSiON but much lower Vt, greatly-improved PBTI and 150times lower J_g wrt SiON. By demonstrating a novel DyO cap layer selective removal process, this work also points out the feasibility to realize low V_t CMOS using either dual phase (NiSi, Ni₃₂Si₁₂) or single phase (Ni₂Si) FUSI gate for both n-and pFETs.

Switching mechanism in two-terminal vanadium dioxide devices

Two-terminal thin film VO2 devices show an abrupt decrease of resistance when the current or voltage applied exceeds a threshold value. This phenomenon is often described as a field-induced metal-insulator transition. We fabricate nano-scale devices with different electrode separations down to 100 nm and study how the dc switching voltage and current depend on device size and temperature. Our observations are consistent with a Joule heating mechanism governing the switching. Pulsed measurements show a switching time to the high resistance state of the order of one hundred nanoseconds, consistent with heat dissipation time. In spite of the Joule heating mechanism which is expected to induce device degradation, devices can be switched for more than 10(10) cycles making VO2 a promising material for nanoelectronic applications.

Implementing cubic-phase HfO 2 with κ-value ∼ 30 in low-V T replacement gate pMOS devices for improved EOT-Scaling and reliability

Higher κ-value HfO₂ (κ~30) was evaluated in replacement metal gate pMOS devices. The higher-κ was achieved by doping and anneal of the HfO₂ causing crystallization into the cubic phase. The resulting gate-stack has up to 10³ × lower gate-leakage current compared to a reference HfO₂: J_G at -1 V ~ 2 μA/cm² at EOT~9.7 Å. The better J_G - EOT-scaling, result in performance and reliability improvements when normalized to the J_G.

Optimization of low temperature silicon nitride processes for improvement of device performance

This paper gives some insights in the applications where PECVD nitrides can be introduced to replace the LPCVD layers and how the process parameters need to be varied to obtain the desired properties. Film properties like stress, hydrogen content, wet etch rate and deposition rate are reported. The nitrides are optimized for specific applications and examples on the influence of nitride properties on device performance are given. It is important to investigate that the advantage of the high film integrity of nitride layers used in the past is not lost due to the strong demand for developing new process schemes with low thermal budget layers. We show that PECVD films are a valid alternative for LPCVD and that the majority of the film properties satisfy the criteria to use PECVD films as contact-etch-stop layers, silicidation blocking films and spacer materials.

Demonstration of Ni fully germanosilicide as a pFET gate electrode candidate on HfSiON

We report for the first time on the use of a Ni fully germano-silicide (FUGESI) as a metal gate in pFETs. Using HfSiON dielectrics and comparing to Ni FUSI devices, we demonstrate that the addition of Ge in poly-Si gate results in 1) Fermi-level unpinning with >200 mV increase in work function; 2) improved dielectrics integrity: such as decreased 1/f and generation-recombination noise, improved channel interface, reduced gate leakage, and superior NBTI characteristics. The above experimental observations are correlated to oxygen vacancies related defects in the HfSiON layer

Novel junction design for NMOS Si Bulk-FinFETs with extension doping by PEALD phosphorus doped silicate glass

We demonstrate a NMOS Si Bulk-FinFET with extension doped by Phosphorus doped Silicate Glass (PSG). Highly doped PSG (6e21 cm^-3) was used as a diffusion source. SiO₂ cap on PSG decreased sheet resistance (Rs) due to less out diffusion of P. Even when thin SiO₂ exists at the interface between Si and PSG, P diffused from PSG into Si. Thanks to the high etch rate of the PSG/SiO₂ cap stack after drive-in anneal, the PSG/SiO₂ cap was successfully removed by HF with minimum removal of STI and gate hard mask oxide. PSG provides damage free and uniform sidewall doping to fin. On current I_ON is improved by 20% for L_G in the 30-24 nm range, with similar I_OFF and better DIBL compared to P ion implanted reference.