Yeow Kheng Lim

Optimization of the Thermomechanical Reliability of a 65 nm Cu/Low-

The trend toward finer pitch and higher performance integrated circuit devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermomechanical failure is one of the major bottlenecks in the development of Cu/low-k larger-die flip chip packages. This paper describes the optimization of the structural design of Chartereds C65 nm 21 mm times 21 mm die size flip-chip ball grid array package incorporated with fully active and functional ninemetal Cu/low-k layers and 150 mum interconnect pitch. The lowk material used in this paper is nonporous SiCOH with a k value of 2.9. A parametric study using 2-D plane strain finite element analysis was performed to study the effect of various parameters on the reliability of the large-die package in order to arrive at an optimized design. In order to have a simple criterion to predict the reliability of the yet-to-be-built largedie package, reliability tests were carried out on some existing 15 mm times 15 mm die CvJlow-k flip chip packages which were identical to the 21mm times 21mm die package except for the size. The packages were found to pass the reliability tests. 2-D plane strain finite element analyses were then performed on the 15 mm times 15 mm die. The computed delamination stresses at the low-k layer and the strain energy density dissipation per cycle in the critical solder (DeltaW) were then used as a benchmark for the design of a larger flip chip package. The efficacy of the polymer encapsulated dicing lane technology was established. In this paper, the effect of the number of fluorosilicate glass layers, die thickness, substrate thickness, Cu post height, and underfill type on the delamination stresses in the low-k layer and DeltaW were determined. Specimens of the optimized large-die package were then fabricated and subjected to reliability tests. They were all found to pass the reliability tests. From these reliability tests, new benchmark values of the delamination stresses at the low-k layer and DeltaW are obtained, which can be used to aid in the design of large-die Cu/low-k flip chip packages.

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Abstract A systematic underfill selection approach has been presented to characterize and identify suitable underfill encapsulants for large size flip chip ball grid array (FCBGA) packages. In the selection scheme, a total of six evaluation factors such as fracture toughness, coefficient of moisture expansion, flowability, delamination performance and filler settlement were considered. Driving stresses for package failure were also included as a factor of consideration, which clearly depends on the package size and geometry. Based on the approach adopted, underfill material that is suitable for 35xa0×xa035xa0mm2 packages with 15xa0mm die size and 45xa0×xa045xa0mm2 packages with 21xa0mm die size was selected. Target value for underfill properties has also been revised.

Large-Die Flip Chip Package

Abstract This paper reports the design, assembly and reliability assessment of 21xa0×xa021xa0mm 2 Cu/low- k flip chip (65xa0nm node) with 150xa0μm bump pitch and high bump density. To reduce the stress from the solder bump pad to low- k layers, Metal Redistribution Layer (RDL) and Polymer Encapsulated Dicing Lane (PEDL) are applied to the Cu/low- k wafer. Lead-free Sn2.5Ag, high-lead Pb5Sn and Cu-post/Sn37Pb bumps are evaluated as the first-level interconnects. It is found that the flip chip assembly of high-lead bumped test vehicle requires the right choice of flux and good alignment between the high-lead solder bumps and substrate pre-solder alloy to ensure proper solder bump and substrate pre-solder alloy wetting. Joint Electron Device Engineering Council (JEDEC) standard reliability is performed on the test vehicle with different first-level interconnects, underfill materials and PEDL. By integrating PEDL to the Cu/low- k chip, the reliability performance of the flip chip package has been improved by almost two times. This paper has demonstrated Moisture Sensitivity Test-Level 2 (MST-L2) qualified large die and fine-pitch Cu/low- k flip chip package. The presented results are significant for the development of flip chip packaging technologies for future advanced Cu/low- k generations.

Underfill selection methodology for fine pitch Cu/low-k FCBGA packages

In this paper, a systematic underfill selection approach has been presented to characterize and identify favorable underfill encapsulants for 21 times 21 mm2 flip chip ball grid array (FCBGA) package with 150 mum interconnect pitch. A total of six evaluation factors of equal ranking weightage were considered in this underfill selection approach. Based on the approach adopted, we have selected the best underfill material suitable for 15 times 15 mm2 FCBGA packages. The target property ranges for underfill materials proposed by the IBM are further being refined. Now, a wider choice of underfill material was found to be applicable for 15 times 15 mm2 FCBGA packages. The new approach has helped to widen the selection criteria for underfill material used in 15 times 15 mm2 FCBGA packages. These findings will assist researchers in having a wider option in underfill selection for future FCBGA packages, which are more challenging.

Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package

An overview of the semiconductor roadmap of interconnects process transition from 0.13mum to 45nm using current proven state- of-the-art manufacturing technology in relation to the integration of dielectric material progressing from fluorinated silica glass to porous low-k will be discussed. Key challenges of process integration with shrinking dimension to meet the ever-demanding timing delay due to interconnects will be shown. Process enhancements with design for manufacturing concepts are addressed to meet the industrial specifications of reliability and chip package interaction for mass production.

A Systematic Underfill Selection Methodology for Fine Pitch Cu/Low-k FCBGA Package

The trend toward finer pitch and higher performance integrated circuits (ICs) devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermo-mechanical failure is one of the major bottlenecks for development of a Cu/low-k larger die flip chip package. Very low modulus underfills must also be avoided because low modulus underfills transfer too much stress to the bumps which result in bump cracking in TC testing. A 2D plane strain analysis was performed to investigate the reliability of Chartereds C 65 nm 21 x 2 lmm 9 metal Cu/ low-k, chips with 150 um interconnect pitch in a FCBGA package. A series of parametric studies are performed by using Polymer Encapsulated Dicing Lane Technology (PEDL) to reduce 1 layer of FSG, variation of Cu post height, die thickness, substrate thickness, and underfill selection. The results obtained from the reduction of the stress in the low-k structure and the inelastic energy in the solder bumps modeling is useful to formulate design guidelines for packaging of large dies.

BEOL Advance Interconnect Technology Overview and Challenges

The trend toward finer pitch and higher performance integrated circuits (ICs) devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermo-mechanical failure is one of the major bottlenecks for development of fine-pitch, large-die Cu/low-k flip chip packages. In this paper, 3D finite element analyses were performed to investigate the reliability of 65 nm, 21times21 mm 9metal Cu/ low-k, chips with 150 mum interconnect pitch in a FCBGA package with a 750 mum die thickness and 1.0 mm substrate thickness. Three parametric cases involving different geometries of solder joints were analyze: (A) All 20 rows with spherical solder joints, (B) 10 hourglass joints followed by 10 spherical joints, and (C) 10 spherical joints followed by 10 hourglass joints. The spherical joints are stiffer than the hourglass joints. It was found that Case C gave the lowest inelastic energy dissipation (DeltaW) for the critical solder joint implying that Case C will have the longest fatigue life. It was also found that Case C gave the lowest maximum stress in the low-k material and it was further shown that reliability will be enhanced with decrease in die thickness and substrate thickness.

Structural Design and Optimization of 65nm Cu/low-k Flipchip Package

This paper focused on design, assembly and reliability assessments of 21 × 21 mm2 Cu/Low-K Flip Chip (65 nm technology) with 150 ¿m bump pitch. Metal redistribution layer (RDL) and polymer encapsulated dicing lane (PEDL) were applied to the chip wafer to reduce the shear stress on the Cu/low-K layers and also the strain on the solder bumps. The first level interconnects evaluated were Pb-free (97.5Sn2.5Ag), High-Pb (95Pb5Sn) and Cu-post/95Pb5Sn. Two different die thicknesses, such as 750 ¿m and 300 ¿m, were evaluated. the flip chip assembly of high-pb test vehicles required the right choice of flux and special alignment between the high-pb solder bumps and substrate presolder to ensure proper solder bumps and substrate pre-solder alloy wetting. Finite Element Modeling (FEM) was performed to investigate the impact of different underfill, on the inelastic strain of the outermost bumps and shear stress in the Cu/low-K layer. JEDEC standard reliability were performed on the test vehicles with different first level interconnects, die thickness, underfill materials and dicing methods.