Ravi Prakash Srivastava

Plasma etch challenges for porous low-k materials for 32nm and beyond

The challenges facing back-end-of-line (BEOL) etch as technology nodes progress are becoming increasingly difficult as the challenges due to shrinking dimensions are compounded by the challenges from new materials integration. Materials 100nm, new interactions of the materials with this critical dimension need to be considered. Both single and multipatterning schemes are considered, with some of the new challenges due to the multi-patterning schemes being highlighted. The need for a trench-first-via-last patterning scheme will also be reviewed in the context of advanced patterning nodes where Mx-to-Vx-1 spacing, via chamfering, and metal fill compatibility are key concerns. In addition, for trench double patterning, there is increased focus on the same-color tip-to-tip and tip-to-side rules, requiring etch to focus on CD control capabilities not only for the line CD but also for the line end, and line ends have always been a key challenge for k ≤ 2.55 etching, where metallization is most sensitive to dielectric damage structural effects. This paper will review several different patterning approaches and analyze the etch challenges as a function of dimensions, materials, or a combination of both.

Process variation challenges and resolution in the negative-tone develop double patterning for 20nm and below technology node

Immersion based 20nm technology node and below becoming very challenging to chip designers, process and integration due to multiple patterning to integrate one design layer . Negative tone development (NTD) processes have been well accepted by industry experts for enabling technologies 20 nm and below. 193i double patterning is the technology solution for pitch down to 80 nm. This imposes tight control in critical dimension(CD) variation in double patterning where design patterns are decomposed in two different masks such as in litho-etch-litho etch (LELE). CD bimodality has been widely studied in LELE double patterning. A portion of CD tolerance budget is significantly consumed by variations in CD in double patterning. The objective of this work is to study the process variation challenges and resolution in the Negative Tone Develop Process for 20 nm and Below Technology Node. This paper describes the effect of dose slope on CD variation in negative tone develop LELE process. This effect becomes even more challenging with standalone NTD developer process due to q-time driven CD variation. We studied impact of different stacks with combination of binary and attenuated phase shift mask and estimated dose slope contribution individually from stack and mask type. Mask 3D simulation was carried out to understand theoretical aspect. In order to meet the minimum insulator requirement for the worst case on wafer the overlay and critical dimension uniformity (CDU) budget margins have slimmed. Besides the litho process and tool control using enhanced metrology feedback, the variation control has other dependencies too. Color balancing between the two masks in LELE is helpful in countering effects such as iso-dense bias, and pattern shifting. Dummy insertion and the improved decomposition techniques [2] using multiple lower priority constraints can help to a great extent. Innovative color aware routing techniques [3] can also help with achieving more uniform density and color balanced layouts.

From Process Assumptions to Development to Manufacturing

A tool has been developed that can be used to characterize or validate a BEOL interconnect technology. It connects various process assumptions directly to electrical parameters including resistance. The resistance of narrow copper lines is becoming a challenging parameter, not only in terms of controlling its value but also understanding the underlying mechanisms. The resistance was measured for 45nm-node interconnects and compared to the theory of electron scattering. This work will demonstrate how valuable it is to directly link the electrical models to the physical on-wafer dimensions and in turn to the process assumptions. For example, one can generate a tolerance pareto for physical and or electrical parameters that immediately identifies those process sectors that have the largest contribution to the overall tolerance. It also can be used to easily generate resistance versus capacitance plots which provide a good BEOL performance gauge. Several examples for 45nm BEOL will be given to demonstrate the value of these tools.