Hui Peng Koh

EUV OPC for the 20-nm node and beyond

Although the k1 factor is large for extreme ultraviolet (EUV) lithography compared to deep ultraviolet (DUV) lithography, OPC is still needed to print the intended patterns on the wafer. This is primarily because of new non-idealities, related to the inability of materials to absorb, reflect, or refract light well at 13.5nm, which must be corrected by OPC. So, for EUV, OPC is much more than conventional optical proximity correction. This work will focus on EUV OPC error sources in the context of an EUV OPC specific error budget for future technology nodes. The three error sources considered in this paper are flare, horizontal and vertical print differences, and mask writing errors. The OPC flow and computation requirements of EUV OPC are analyzed as well and compared to DUV. Conventional optical proximity correction is simpler and faster for EUV compared to DUV because of the larger k1 factor. But, flare and H-V biasing make exploitation of design hierarchy more difficult.

Integration of an EUV metal layer: a 20/14nm demo

EUV technology has steadily progressed over the years including the introduction of a pre-production NXE:3100 scanner that has enabled EUV process development to advance one step closer to production. We have carried out the integration with 20/14nm metal layer design rules converting double patterning with ArF immersion process to EUV with a single patterning solution utilizing a NXE3100 exposure tool. The exercise through the integration of a mature test chip with an EUV level has allowed us to have early assessment of the process challenges and new workflow required to enable EUV to the mass production stage. Utilizing the NXE3100 in IMEC, we have developed an OPC model and a lithography process to support 20/14nm node EUV wafer integration of a metal layer in conjunction with immersion ArF. This allows early assessment of mix-and-match overlay for EUV to immersion system that is critical for EUV insertion strategy as well as further understanding of the litho process, OPC, and mask defect control specific to EUV single patterning. Through this work we have demonstrated high wafer yields on a 20nm test vehicle utilizing single EUV Metal layer along with additional ArF immersion levels. We were able to successfully demonstrate low mask defectivity and good via chain and open/short electrical yield. This paper summarize the learning cycles from mask defect mitigation and mix machine overlay through post metal CMP wafer integration highlighting the key accomplishments and future challenges.

A novel method to reduce wafer topography effect for implant lithography process

Wafer topography structures in the implant lithography process, which include the shallow trench isolation and the poly gate, can result into a severe degradation of the resist profile and significant critical dimension variation. While bottom anti-reflective coating (BARC) is not suitable for the implant lithography because of the plasma induced substrate damage, developable bottom anti-reflective coating (DBARC) is now the most promising solution to eliminate wafer topography effects for the implant layer lithography. Currently, some challenges still remain to be solved and DBARC is not ready for mass production yet. In this study, a novel method is proposed to improve wafer topography effects by use of sub-resolution features. Compared with DBARC, this new approach is much more cost effective. Numerical study by use of Sentaurus-Litho simulation tool shows that the new method is promising and deserves more comprehensive investigation.

Process variation challenges and resolution in the negative-tone develop double patterning for 20nm and below technology node

Immersion based 20nm technology node and below becoming very challenging to chip designers, process and integration due to multiple patterning to integrate one design layer . Negative tone development (NTD) processes have been well accepted by industry experts for enabling technologies 20 nm and below. 193i double patterning is the technology solution for pitch down to 80 nm. This imposes tight control in critical dimension(CD) variation in double patterning where design patterns are decomposed in two different masks such as in litho-etch-litho etch (LELE). CD bimodality has been widely studied in LELE double patterning. A portion of CD tolerance budget is significantly consumed by variations in CD in double patterning. The objective of this work is to study the process variation challenges and resolution in the Negative Tone Develop Process for 20 nm and Below Technology Node. This paper describes the effect of dose slope on CD variation in negative tone develop LELE process. This effect becomes even more challenging with standalone NTD developer process due to q-time driven CD variation. We studied impact of different stacks with combination of binary and attenuated phase shift mask and estimated dose slope contribution individually from stack and mask type. Mask 3D simulation was carried out to understand theoretical aspect. In order to meet the minimum insulator requirement for the worst case on wafer the overlay and critical dimension uniformity (CDU) budget margins have slimmed. Besides the litho process and tool control using enhanced metrology feedback, the variation control has other dependencies too. Color balancing between the two masks in LELE is helpful in countering effects such as iso-dense bias, and pattern shifting. Dummy insertion and the improved decomposition techniques [2] using multiple lower priority constraints can help to a great extent. Innovative color aware routing techniques [3] can also help with achieving more uniform density and color balanced layouts.

Best-practice evaluation-methods for wafer-fab photomask-requalification inspection tools

Requalifying semiconductor photomasks remains critically important and is increasingly challenging for 20nm and 14nm node logic reticles. Patterns are becoming more complex on the photomask, and defect sensitivity requirements are more stringent than ever before. Reticle inspection tools are equally important for effective process development and the successful ramp and sustained yield for high volume manufacturing. The inspection stages considered were: incoming inspection to match with Mask Shop Outgoing result and to detect defects generated during transport; requalification by routine cycle inspection to detect Haze and any other defects; and inspection by in-house or Mask shop at the post cleaning. There are many critical capability and capacity factors for the decision for best inspection tool and strategy for high volume manufacturing, especially objective Lens NA, wavelength, power, pixel size, throughput, full-automation inspection linked with Overhead Transport, algorithm application, engineering application function, and inspection of PSM and OMOG . These tools are expensive but deliver differentiated value in terms of performance and throughput as well as extendibility. Performing a thorough evaluation and making a technically sound choice which explores these many factors is critical for success of a fab. This paper examines the methodology for evaluating two different photomask inspection tools. The focus is on ensuring production worthiness on real and advanced product photomasks requiring accurate evaluation of sensitivity, throughput, data analysis function and engineering work function on those product photomasks. Photomasks used for data collection are production reticles, PDM(Program defect Mask), SiN spray defect Reticle which is described that evaluates how the tools would perform on a contaminated plate.

Fourier spectrum method to determine dose-to-clear in a photoresist.

A Fourier spectrum method to determine the dose-to-clear in a photoresist is proposed. The frequency content of scanning electron microscope resist images is used to determine whether the resist has been dissolved. Using this method, the dose to clear the resist is calculated automatically instead of via visual inspection, a method in which operator influence can affect the result.

7nm node EUV predictive study of mask LER transference to wafer

The transition into smaller nodes has resulted in stringent CD tolerance requirements and the role of mask LER in that budget is not sufficiently understood. The critical variables associated with mask LER were explored with the goal of establishing mask requirements based on wafer requirements. A systematic study of the impact of mask LER correlation length (ξ), critical exponent (α) and standard deviation of the line edge (σ) on the printability of 7nm node line/space (L/S) and contact holes (CH) in extreme ultraviolet lithography has been simulated. An experimentally relevant range of the three mask LER variables was explored in these simulations. CDU and CER/LER were the primary metrics used to gauge printability and they were evaluated as a function of ξ, α and σ with stochastic simulations. A 45nm pitch was investigated to determine critical mask LER parameters that mark printability transition regions relevant to the 7nm node middle of line.

Investigation of trench and contact hole shrink mechanism in the negative tone develop process

The objective of this work was to study the trench and contact hole shrink mechanism in negative tone develop resist processes and its manufacturability challenges associated for 20nm technology nodes and beyond. Process delay from post-exposure to develop, or “queue time”, is studied in detail. The impact of time link delay on resolved critical dimension (CD) is fully characterized for patterned resist and etched geometries as a function of various process changes. In this study, we assembled a detailed, theoretical model and performed experimental work to correlated time link delay to acid diffusion within the resist polymer matrix. Acid diffusion is determined using both a modulation transfer function for diffusion and simple approximation based on Fick’s law of diffusion.

Review of resist-based flare measurement methods for extreme ultraviolet lithography

Abstract. Flare (stray light) is an important effect impacting extreme ultraviolet lithography (EUVL) imaging system performance. Four flare measurement methods including Kirk, modulation transfer function, double exposure, and zonal ring approximation method are reviewed and analyzed theoretically. The point spread function of an EUV NXE:3100 exposure tool is extracted from the measured Kirk flare (KF) and fitted with a double-fractal model. The KF for this NXE:3100 tool is determined to be 8.5% for a 2-μm diameter absorber pad placed in a 12-mm outer radius bright field, which is larger than the previous 5% KF data measured by ASML and IMEC in 2011. The observation of the increased flare level in the NXE:3100 tool suggests that contamination of EUV optics may be a potential problem for EUVL manufacturing.

20nm MOL overlay case study

As the process nodes continue to shrink, overlay budgets are approaching theoretical performance of the tools. It becomes even more imperative to improve overlay performance in order to maintain the roadmap for advance integrated circuit manufacturing. One of the critical factors in 20nm manufacturing is the overlay performance between the Middle of Line (MOL) and the Poly layer. The margin between these two layers was a process limiter, it was essential that we maintain a very tight overlay control between these layers. Due to various process and metrology related effects, maintaining good overlay control became a challenge. In this paper we describe the various factors affecting overlay performance and the measures taken to mitigate or eliminate said factors to improve overlay performance.