Sohrab Emami

Millimeter-wave CMOS design

This paper describes the design and modeling of CMOS transistors, integrated passives, and circuit blocks at millimeter-wave (mm-wave) frequencies. The effects of parasitics on the high-frequency performance of 130-nm CMOS transistors are investigated, and a peak f/sub max/ of 135 GHz has been achieved with optimal device layout. The inductive quality factor (Q/sub L/) is proposed as a more representative metric for transmission lines, and for a standard CMOS back-end process, coplanar waveguide (CPW) lines are determined to possess a higher Q/sub L/ than microstrip lines. Techniques for accurate modeling of active and passive components at mm-wave frequencies are presented. The proposed methodology was used to design two wideband mm-wave CMOS amplifiers operating at 40 GHz and 60 GHz. The 40-GHz amplifier achieves a peak |S/sub 21/| = 19 dB, output P/sub 1dB/ = -0.9 dBm, IIP3 = -7.4 dBm, and consumes 24 mA from a 1.5-V supply. The 60-GHz amplifier achieves a peak |S/sub 21/| = 12 dB, output P/sub 1dB/ = +2.0 dBm, NF = 8.8 dB, and consumes 36 mA from a 1.5-V supply. The amplifiers were fabricated in a standard 130-nm 6-metal layer bulk-CMOS process, demonstrating that complex mm-wave circuits are possible in todays mainstream CMOS technologies.

Design considerations for 60 GHz CMOS radios

With the availability of 7 GHz of unlicensed spectrum around 60 GHz, there is a growing interest in using this resource for new consumer applications requiring very high-data-rate wireless transmission. Historically, the cost of the 60 GHz electronics, implemented in the compound semiconductor technology, has been prohibitively expensive. A fully integrated CMOS solution has the potential to drastically reduce costs enough to hit consumer price points. System, circuit, and device-level barriers to a low-cost 60 GHz CMOS implementation are described, potential solutions are explored, and remaining challenges are discussed.

A 60GHz CMOS phased-array transceiver pair for multi-Gb/s wireless communications

Recent advances in silicon technology, mm-Wave integrated circuit/antenna/package design, and beam-forming techniques at 60GHz, together with the emergence of suitable wireless standards, have enabled consumer electronics products to support wireless transmission of multi-Gb/s data such as high-definition (HD) audio/video content [1,2]. Further expansion into portable and mobile platforms will require lower power consumption, smaller form factor, and lower cost. This paper describes a fully integrated, low-cost 60GHz phased-array transceiver pair, implemented in 65nm standard digital CMOS and packaged with an embedded antenna array, capable of robust 10m non-line of sight (NLOS) communication. The array is configurable from 32 elements to 8 or fewer elements, making the transceiver pair suitable for both fixed, high-data-rate and portable, low-power applications. To enhance the robustness of the multi-element design, dynamic phase shifters allow the beam direction to be changed in real time to adapt to changing environments without interruption of the multi-Gb/s data stream. The transceiver pair supports the WirelessHD and draft 802.11ad (WiGig) standards at maximum data rates of 7.14Gb/s and 6.76Gb/s, respectively.

Design of CMOS for 60GHz applications

The viability of digital CMOS as a future mm-wave technology, capable of exploiting the 60GHz band, is explored. Optimal device design and appropriate mm-wave models are presented. From modeling of transistors in 0.13/spl mu/m technology a three cascode-stage amplifier at 1.5 volts would provide 11 dB of gain at 60GHz using 54mW.

A Highly Integrated 60GHz CMOS Front-End Receiver

A 60GHz CMOS front-end receiver is described. The receiver comprises an LNA, a quadrature-balanced downconversion mixer, a VCO, and a frequency doubler. The integrated front-end has a conversion gain of 11.8dB, an NF of 10.4dB, and an input P1dB of -15.8dBm. The receiver is implemented in a digital 0.13mum CMOS process and draws 64mA from a 1.2V supply.

A 60-GHz down-converting CMOS single-gate mixer

A quadrature balanced single-gate CMOS mixer, designed to exploit the unlicensed band around 60-GHz, is presented. Also a millimeter-wave (mm-wave) modeling methodology is discussed which is suitable for the design of CMOS mm-wave active mixers. The performance of a fully-integrated mixer fabricated on a standard digital 130-nm CMOS process is given and compared to the simulations. At a radio frequency (RF) of 60 GHz, intermediate frequency (IF) of 2 GHz, and low LO power of 0 dBm, conversion loss is better than 2 dB, and an input-referred 1-dB compression point of -3.5 dBm was measured.

60 GHz CMOS radio for Gb/s wireless LAN

The availability of 7 GHz of unlicensed spectrum in the 60 GHz band motivates the design of a low-cost 60 GHz wireless LAN (WLAN) system. System and circuit barriers to a low cost implementation are discussed and various solutions are proposed.

Large-signal millimeter-wave CMOS modeling with BSIM3

A large-signal modeling methodology based upon a modified BSIM3v3 transistor model is presented which targets MM-wave CMOS applications. The effect of parasitics on the high-frequency operation of CMOS transistors is discussed, and a standard intrinsic BSIM3v3 model card is augmented with lumped elements to model these effects. Core BSIM parameters are extracted to match the measured DC I-V curves of a fabricated common-source NMOS transistor. Measured S-parameters are used to extract external parasitic component values to obtain a bias-dependent small-signal MM-wave frequency fit up to 65 GHz. The large-signal MM-wave accuracy of the model is verified by measuring the output harmonics power under large-signal excitation. Comparisons of measurements with the simulations show good agreement up to 60 GHz.

Nanoscale CMOS for mm-Wave Applications

Aggressive technology scaling of CMOS has culminated in a low-cost high volume commercial process technology with Ft > 150 GHz and Fmax > 200 GHz. This paper discusses the key trends in CMOS scaling that have led to this level of performance and attempts to predict the performance down to 45 nm. The design of active and passive components in CMOS for power gain and low noise are discussed in detail and unique features of CMOS technology are highlighted. Experimental results derived from a 60 GHz amplifier in 90 nm CMOS and a complete 60 GHz front-end receiver in 130 nm CMOS are reported.

Millimeter-wave CMOS device modeling and simulation

Challenges for modeling and simulating active and passive 130 nm CMOS devices at mm-wave frequencies (>30 GHz) are discussed. Small-signal lumped circuits with appropriate parasitic elements are used to model the active transistor devices with excellent broadband accuracy. Passive element transmission lines are discussed as generic scalable reactive elements suitable for forming resonant circuits with intrinsic transistor capacitance. The trade-offs between physical and electrical circuit models for the transmission lines are presented. Our approach demonstrates that relatively simple models can be used to accurately predict the small-signal performance of CMOS active and passive devices from DC up to mm-wave frequencies.