Soner Yaldiz

A Linearized, Low-Phase-Noise VCO-Based 25-GHz PLL With Autonomic Biasing

This paper describes a new approach to low-phasenoise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase noise of - 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 1500 measurements of the PLL across PVT variations were taken, further validating the proposed design. Phase noise variation across 55 dies for four different frequencies is σ < 0.6 dB. Also, phase noise variation across supply voltages of 0.7-1.5 V is 2 dB and across 60 °C temperature variation is 3 dB. At the 25 GHz center frequency, the VCO FOMT is 188 dBc/Hz. Additionally, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results indicate the efficacy of the autonomic biasing scheme.

SRAM parametric failure analysis

With aggressive technology scaling, SRAM design has been seriously challenged by the difficulties in analyzing rare failure events. In this paper we propose to create statistical performance models with accuracy sufficient to facilitate probability extraction for SRAM parametric failures. A piecewise modeling technique is first proposed to capture the performance metrics over the large variation space. A controlled sampling scheme and a nested Monte Carlo analysis method are then applied for the failure probability extraction at cell-level and array-level respectively. Our 65nm SRAM example demonstrates that by combining the piecewise model and the fast probability extraction methods, we have significantly accelerated the SRAM failure analysis.

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL

An integral-path self-calibration scheme is introduced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCOs small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4 dB to 1 dB, when measured at 70 sites on a 300 mm wafer. The PLL has a measured phase noise @10 MHz offset of -126.5 dBc/Hz at 20.1 GHz and - 124.2 dBc/Hz at 24 GHz

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion

On-chip analog self-healing requires low-cost sensors to accurately measure various performance metrics. In this paper we propose a novel approach of indirect performance sensing based upon Bayesian model fusion (BMF) to facilitate inexpensive-yet-accurate on-chip performance measurement. A 25GHz differential Colpitts voltage-controlled oscillator (VCO) designed in a 32nm CMOS SOI process is used to validate the proposed indirect performance sensing and self-healing methodology. Our silicon measurement results demonstrate that the parametric yield of the VCO is improved from 0% to 69.17% for a wafer after the proposed self-healing is applied.

Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits

The advent of the nanoscale integrated circuit (IC) technology makes high performance analog and RF circuits increasingly susceptible to large-scale process variations. On-chip self-healing has been proposed as a promising remedy to address the variability issue. The key idea of on-chip self-healing is to adaptively adjust a set of on-chip tuning knobs (e.g., bias voltage) in order to satisfy all performance specifications. One major challenge with on-chip self-healing is to efficiently implement on-chip sensors to accurately measure various analog and RF performance metrics. In this paper, we propose a novel indirect performance sensing technique to facilitate inexpensive-yet-accurate on-chip performance measurement. Towards this goal, several advanced statistical algorithms (i.e., sparse regression and Bayesian inference) are adopted from the statistics community. A 25 GHz differential Colpitts voltage-controlled oscillator (VCO) designed in a 32 nm CMOS SOI process is used to validate the proposed indirect performance sensing and self-healing methodology. Our silicon measurement results demonstrate that the parametric yield of the VCO is significantly improved for a wafer after the proposed self-healing is applied.

Indirect phase noise sensing for self-healing voltage controlled oscillators

The push for higher performance analog/RF circuits in scaled CMOS necessitates self-healing via post-manufacturing tuning. A major challenge with self-healing systems is the efficient design of on-chip sensors that capture the performance of interest. This is particularly difficult for metrics such as phase noise that are not easily measured on-chip. We propose an indirect sensing method that exploits the correlations between the performance metrics of interest and those that can be measured using easy-to-integrate sensors. We demonstrate indirect phase noise sensing for a 25GHz self-healing voltage controlled oscillator (VCO) design in 32nm CMOS SOI that approaches the best parametric yield achievable based on simulated results.

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS

A 23.5 GHz 32 nm SOI-CMOS PLL with 30% frequency tuning range features an adaptively biased VCO. The adaptive biasing scheme lowers the average PLL power consumption from 34 mW to 27.2 mW, while keeping the jitter below 1.3° RMS across all frequency bands.

Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study

This paper presents a novel stochastic modeling and optimization framework for energy minimization in multicore systems running real-time applications with tolerance to deadline misses. This framework is based on stochastic application models, which capture the variability of and the spatial and temporal correlations among the workloads of concurrent and interdependent tasks that constitute the application. These stochastic models are utilized in novel mathematical formulations to obtain optimal energy management policies. Experimental results on MPEG2 video decoding show that significant energy savings can be achieved, often close to the theoretical upper bound.

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS

A 30% frequency tuning range 23.5GHz 32nm SOI-CMOS PLL features an adaptively biased VCO. Adaptive biasing of the VCO lowers the average PLL power consumption from 34mW to 24mW, while keeping the jitter below 1.5° RMS across all frequency bands.

Efficient statistical analysis of read timing failures in SRAM circuits

A system-level statistical analysis methodology is described that captures the impact of inter- and intra-die process variations for read timing failures in SRAM circuit blocks. Unlike existing approaches that focus on cell-level performance metrics for isolated sub-components or ignore inter-die variability, the system-level performance is accurately predicted for the entire SRAM circuit that is impractical to analyze statistically via transistor-level Monte Carlo simulations. The accurate bounding of read timing failures using this methodology is validated with silicon measurements from a 64kb SRAM testchip in 90nm CMOS. We demonstrate the efficacy of this methodology for earlystage design exploration to specify redundancy, required sense amp offset, and other circuit choices as a function of memory size.