Soo-Geun Lee

Static noise margin of the full DG-CMOS SRAM cell using bulk FinFETs (Omega MOSFETs)

The operational six-transistor SRAM cell was experimentally demonstrated using bulk FinFET CMOS technology. A cell size of 0.79 /spl mu/m/sup 2/ was achieved by 90 nm node technology, with stable operation at 1.2 V using 4 levels of W and Al interconnects. Static noise margin of 280 mV was obtained at V/sub cc/ of 1.2 V. To our knowledge, this represents the first experimental demonstration of a fully integrated bulk FinFET SRAM cell.

New insight into stress induced voiding mechanism in Cu interconnects

An effective method was used for the failure analysis of stress induced voids. Instead of conventional vertical inspection, the lower wide copper surface connected to the via was investigated after removing the passivation layer and upper copper layer. Many voids were observed at the grain boundary area, regardless of via location. According to the step by step inspection of that surface, many small voids were generated at the grain boundary area after dielectric barrier deposition, even before an HTS (high temperature storage) test, and some of the voids were grown after HTS, preferentially at the grain boundary corners. This result implies that unlucky landing of via over the grain boundary area would be the main cause of stress induced void under the via.

Integration and reliability of a noble TiZr/TiZrN alloy barrier for Cu/low-k interconnects

We have investigated TiZr alloy as a new Cu barrier material for low cost and high performance Cu/low-k interconnects. TiZrN ternary nitride was used as a Cu diffusion barrier and TiZr as an adhesion promotion layer. The issue of metal line resistance shift was suppressed using a novel 2-step annealing procedure. Multi-level Cu metal wiring integration was successfully carried out and the enhanced electrical performance of low via resistance with high via yield was obtained. Improved electromigration and stress-induced voiding resistances also have been demonstrated.

Novel PZT Capacitor Technology for 32Mb and Beyond FRAM Device Using PbTiO 3 Seeding Layer

Effects of the PbTiO 3 (PTO) seeding layer on lowering the PZT crystallization temperature and reducing the capacitor stack height, especially PZT thin film, were systematically investigated. For these purposes, PZT film was modified by using the PTO seeding layer. By using the PTO seeding layer; the crystallization temperature of the PZT film was successfully lowered to 550C. And remanant polarization of PTO-used 100nm thick PZT capacitors measured at 3V was approximately 23 w C/cm 2 , that is 30% higher than that of the PTO-unused PZT capacitors. XRD analysis indicated that the use of the PTO seeding layer remarkably increased the relative intensity of (111) orientation. XRF studies showed that the atomic concentration ratio of Ti-to-Zr was increased by using PTO seeding layers. Necessarily, as the PZT thickness and crystallization temperature are lowered, the thickness of bottom electrode can be reduced as well. Finally, we successfully developed a capacitor stack height of below 400nm, which was composed of Ir/IrO 2 /PZT/Pt/IrO 2 . Furthemore, by lowering the PZT crystallization temperature, small (600 z /contact) and stable contact resistance in a very small size of BC could be obtained.

Stacked FRAM capacitor etching process for high density application

Abstract In this paper, one step ferroelectric capacitor etching technology has been developed. Stacked capacitor layers with 0.75μm height were etched with a TiN hard mask. Etch selectivity increases as oxygen ratio in capacitor etching gases increases. After etching the electrodes and the PZT film, the slope of the stack capacitor was around 72 degrees and it has been proven that no si dew all fence was generated during the capacitor etching process and its leakage current was below 10–6A/cm2. The 0.9×0.9μm2 area capacitor for a 16M FRAM density has been well fabricated by one step etching process with very high selectivity to the mask.

Effects of ILD & IMD characteristics on ferroelectric properties of fram devices

Abstract We have deposited SiO2 using plasma-enhanced TEOS-based (PE-TEOS) CVD method and USG and PSG using atmosphere-pressure CVD method on Pb(Zr, Ti)O3(PZT) capacitors. The ferroelectric and dielectric properties of the SiO2 covered PZT capacitors were characterized. SIMS (secondary ion mass spectroscopy) was utilized to obtain hydrogen concentration in the deposited ILD and IMD materials. The concentration of hydrogen in the PE-TEOS-derived SiO2 was lower than that in the PSG and the USG. Internal stress was low tensile at room temperature and the behavior of thermal stress hysteresis was nearly similar for all SiO2 materials. Remnant polarization (Pr) of the PE-TEOS covered PZT capacitors was severely degraded as compared to that of as-deposited capacitors. From these results, we have concluded that the degradation of ferroelectric characteristics of PZT capacitors associated with the ILD and IMD processes was closely related to the plasma-induced damage.

Cost-effective "BARC/resist-via-fill free" integration technology for 0.13 /spl mu/m Cu/low-k

Demonstrates the first successful integration scheme free of BARC/resist via-fill that not only significantly simplifies the overall process complexity, but also reduces cost and process instabilities by employing an OSG (k=2.9)/ HDP-FSG dual ILD structure in conjunction with our proprietary plasma induced polymeric etch stopper (PIPS) in a 7-metal level 0. 13 /spl mu/m design node. The via poisoning problem and low selectivity of etch stopper were overcome by optimizing ILD structure and PIPS etch process. The electrical characteristics and reliability results indicate that the current integration scheme is highly manufacturable.