Spyridon Vlassis

Low-voltage bulk-driven input stage with improved transconductance

A low-voltage input stage constructed from bulk-driven PMOS transistors is proposed in this paper. It is based on a partial positive feedback and offers significant improvement of both input transconductance and noise performance compared with those achieved by the corresponding already published bulk-driven structures. The proposed input stage offers also extended input common-mode range under low supply voltage in relevant to a gate-driven differential pair. A differential amplifier based on the proposed input stage is also designed, which includes an auxiliary amplifier for the output common-mode voltage stabilization and a latch-up protection circuitry. Both input stage and amplifier circuits were implemented with 1 V supply voltage using standard 0.35µm CMOS process, and their performance evaluation gave very promising results. Copyright

Low-voltage bulk-driven rectifier for biomedical applications

This paper introduces the novel design of a low-voltage low-power voltage rectifier based on bulk-driven (BD) winner-take-all (WTA) circuit. The proposed circuit is able to work as a half- or full-wave rectifier and it is specifically designed for battery-powered implantable and wearable medical devices. The main attractive features of the proposed circuit are topology simplicity, minimal number of transistors, accuracy and capability of rectifying signals with a relatively wide range of frequencies and amplitudes. The circuit was designed with single voltage supply of 0.6V and consumes about 2.14@?W. Detailed simulations using TSMC 0.18@?m n-well CMOS technology were performed to prove the functionality and to fully characterize the circuit performance.

Differential-voltage attenuator based on floating-gate MOS transistors and its applications

In this brief, a very simple differential voltage attenuator based on floating-gate MOS transistors (FGMOS) is proposed. The attenuator constructed by only two stacked identical FGMOS in saturation region, provides a voltage output proportional to the difference of the two input voltages. The advantages of this attenuator are the low supply operation, the rail-to-rail input range with small linearity error and the single-ended input processing. A very efficient technique to transform any circuit that requires only balanced inputs into the single-ended counterpart based on the attenuator, is proposed. Using this technique, a number of single-ended computational circuits are produced such as voltage squarer, four-quadrant multiplier, and vector summation circuit. The circuits can be fabricated in standard double-poly, double-metal CMOS technology and they are suitable for analogue signal processing and neural networks applications. SPICE simulation results using 2-/spl mu/m MIETEC CMOS process parameters demonstrate the feasibility and the accuracy of the circuits.

0.5-V bulk-driven differential amplifier

SUMMARY A new 0.5-V fully differential amplifier is proposed in this article. The structure incorporates a differential bulk-driven voltage follower with conventional gate-driven amplification stages. The bulk-driven voltage follower presents differential gain equal to unity while suppressing the input common-mode voltage. The amplifier operates at a supply voltage of less than 0.5 V, performing input transconductance almost equal to a gate transconductance and relatively high voltage gain without the need for gain boosting. The circuit was designed and simulated using a standard 0.18-µm CMOS n-well process. The low-frequency gain of the amplifier was 56 dB, the unity gain bandwidth was approximately 3.2 MHz, the spot noise was 100 nV/√Hz at 100 kHz and the current consumption was 90 μΑ. Copyright

Sub-Volt Fully Balanced Differential Difference Amplifier

This paper presents a new CMOS structure for a fully balanced differential difference amplifier (FB-DDA) designed to operate from a sub-volt supply. This structure employs the bulk-driven quasi-floating-gate (BD-QFG) technique to achieve the capability of an ultra-low voltage operation and an extended input voltage range. The proposed BD-QFG FB-DDA is suitable for ultra-low-voltage low-power applications. The circuit is designed with a single supply of 0.5 V and consumes only 357 nW of power. The proposed circuit was simulated in a 0.18-μm TSMC CMOS technology and the simulation results prove its functionality and attractive parameters. An application example of a state variable filter is also presented to confirm the usefulness of the proposed BD-QFG FB-DDA.

A CMOS linear-in-dB VGA based on exponential current generator

This paper proposes a simple CMOS exponential current circuit that is capable to control a Variable Gain Amplifier with a linear-in-dB manner. The proposed implementation is based on a Taylors series approximation of the exponential function. A simple VGA architecture has been designed in a CMOS 90nm technology, in order to validate the theoretical analysis. The approximation achieves a 17dB linear range with less than 0.5dB approximation error, while the overall power consumption is less than 300μW.

An interfacing circuit for piezoresistive pressure sensors with frequency output

An interfacing circuit for piezoresistive pressure sensors based on the CMOS operational floating amplifier in a current conveyor configuration is presented. The main advantages of the proposed circuit include the use of only two piezoresistors with high common-mode rejection ratio, using an instrumentation amplifier based on a second-generation current conveyor (CCII) and temperature compensation. The circuit has frequency output proportional to the applied pressure with high linearity and temperature dependence less than 150ppm°C−1. Experimental results, using the interfacing circuit and a commercial silicon pressure sensor, are included to demonstrate its performance.

0.8V bulk-driven variable gain amplifier

A low-voltage variable gain amplifier based on PMOS bulk-driven input stage is presented in this paper. The gain of the proposed amplifier has a linear in-dB gain dependency since it utilizes the conventional pseudo exponential approximation function (1+x)/(1−x). The master-slave technique is used in order to control the voltage gain. The amplifier is designed with a supply voltage of 0.8V featuring a gain range equal to 17dB with less than ±0.5dB linearity error. A standard 0.18µm CMOS process has been chosen to simulate and test the VGA topology confirming the theoretical analysis.

Low-voltage CMOS voltage squarer

A voltage squarer based on bulk-driven PMOS transistors is proposed in this paper. Circuit topology employs a voltage attenuator and the quadratic ID/VG characteristic of a MOS in saturation. The squarer was designed with a 0.8V supply voltage using standard 0.35um CMOS process, which offers large value of threshold voltage. The squarer topology was modified for 0.18um CMOS process, which threshold voltage was smaller, operating under the extreme low supply voltage of 0.5V. The output current is proportional to square of the input voltage in each case. Simulation results verify the theoretical analysis demonstrating small relative error and fast transient response.

Low-voltage differential amplifier

A low-voltage differential amplifier constructed by bulk-driven PMOS transistors is proposed in this paper. A local positive feedback is utilized that boosts the input transconductance and improve the noise performance. The input common-mode range is also compared to the gate-driven counterpart. A 5th order Chebyshev active RC filter with 500 kHz cut-off frequency and 1dB ripple is built based on the proposed amplifier. All circuits were implemented with 1V supply voltage using standard 0.35um CMOS process presenting very promising performances.