V. Kalenteridis

A complete platform and toolset for system implementation on fine-grain reconfigurable hardware

In this paper a complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts: the fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. It is the first such complete academic system. The novel energy efficient FPGA architecture was designed and simulated in STM 0.18 mm CMOS technology. The detailed design and circuit characteristics of the Configurable Logic Block as well as the interconnection network are determined and evaluated for energy, delay and area. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools. q 2004 Elsevier B.V. All rights reserved.

A CMOS linear-in-dB VGA based on exponential current generator

This paper proposes a simple CMOS exponential current circuit that is capable to control a Variable Gain Amplifier with a linear-in-dB manner. The proposed implementation is based on a Taylors series approximation of the exponential function. A simple VGA architecture has been designed in a CMOS 90nm technology, in order to validate the theoretical analysis. The approximation achieves a 17dB linear range with less than 0.5dB approximation error, while the overall power consumption is less than 300μW.

An integrated FPGA design framework: custom designed FPGA platform and application mapping toolset development

Summary form only given. A complete system for the implementation of digital logic in a fine-grain reconfigurable platform is introduced. The system is composed of two parts: The fine-grain reconfigurable hardware platform (FPGA) on which the logic is implemented and the set of CAD tools for mapping logic to the FPGA platform. The novel energy-efficient FPGA architecture was designed and simulated in STM 0.18/spl mu/m CMOS technology. Concerning the tool flow, each tool can operate as a standalone program as well as part of a complete design framework, composed by existing and new tools.

A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications

A complete system for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform is introduced. The novel power-efficient FPGA architecture was designed and simulated in STM 0.18 μm CMOS technology. The detailed design and circuit characteristics of the Configurable Logic Block, the interconnection network, the switch box and the connection box were determined and evaluated in terms of energy, delay and area. A number of circuit-level low-power techniques were employed because power consumption was the primary concern. Additionally, a complete tool framework for the implementation of digital logic circuits in FPGA platforms is introduced. Having as input VHDL description of an application, the framework derives the reconfiguration bitstream of FPGA. The framework consists of: i) non-modified academic tools, ii) modified academic tools and iii) new tools. Furthermore, the framework can support a variety of FPGA architectures. Qualitative and quantitative comparisons with existing academic and commercial architectures and tools are provided, yielding promising results.

AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow

The design of a novel embedded FPGA reconfigurable hardware architecture is introduced. The architecture features a number of circuit-level low-power techniques, since power consumption is considered a primary concern. Additionally, a complete set of tools facilitating implementation of applications on the proposed FPGA was presented, starting from an RTL description and producing the actual configuration bit stream. The designed full-custom FPGA is under fabrication in 0.18/spl mu/m STM CMOS technology. The prototype supports partial and dynamic reconfiguration. The efficiency of the entire system (FPGA and tools) was proven by comparisons with commercial systems.

A complete over-current/short-circuit protection system for Low-Drop Out regulators

A complete over-current and short-circuit protection system for Low-Drop Out (LDO) regulator applications is presented. The system consists of a current-sense circuit, a current comparator, a D Flip-Flop, an OR logic gate and the short-circuit sense topology. The protection circuit is able to shut down the LDO rapidly by producing a control signal when an over-current event occurs while during the normal operation of the LDO, the protection circuit is idle. The restart of the LDO has to be made manually and a master Reset signal is, also, available. The proposed protection system was designed by using a standard 0.18u CMOS technology using high-voltage transistors.

A CMOS linear-in-dB VGA and AGC loop for telecommunication applications

In this paper, an Automatic Gain Control (AGC) loop which is based on a linear-in-dB Variable Gain Amplifier (VGA) is proposed. The VGA structure is based on simple nMOS differential pairs with variable tail currents. The linear-in-dB gain tuning schema is designed using a novel exponential current generator which also offers temperature compensation of the VGAs gain. The gain of the VGA is tuned by a control voltage with gain range about 28dB with Â?1dB linearity error. The worst cases of the VGA gain, over process and temperature corners, are Â?1.54dB and Â?2.45dB for maximum and minimum gain setting, respectively. The proposed implementation is designed in a CMOS 90nm triple-well process with 1.2V supply voltage.

A 60-GHz quadrature PLL in 90nm CMOS

A 1.2 V 60 GHz 120 mW phase-locked loop employing a quadrature differential voltage-controlled oscillator, a programmable charge pump, and a frequency quadrupler is presented. Implemented in a 90 m CMOS process and operating at 60 GHz with a 1.2 V supply, the PLL achieves a phase noise of −91 dBc/Hz at a frequency offset of 1 MHz.

Energy efficient fine-grain reconfigurable hardware

In this paper a novel energy efficient FPGA architecture was designed and simulated in STM 0.18/spl mu/m CMOS technology. The parameters of the configurable logic block architecture have been determined in order to minimize energy consumption. Circuit level low power design techniques are also applied for further reducing energy consumption. In addition, an exploration for the optimum, in terms of energy, delay and area, interconnection routing switches size has been performed.

AGC loop implementation using temperature compensated CMOS linear-in-dB VGA

In this paper, an Automatic Gain Control (AGC) loop is proposed which is based on a linear-in-dB Variable Gain Amplifier (VGA). The VGA structure is based on simple nMOS differential pairs. The linear-in-dB gain tuning schema is designed using a novel exponential generator which it offers also temperature compensation of the VGAs gain. The proposed implementation is designed in 90nm CMOS process with 1.2V supply voltage. The gain of the VGA is tuned by a control voltage with gain range equal to 27dB with ±1dB linearity error. The worst case variations of the VGA gain, over process and temperature corners, are ±1.54dB and ±2.45dB for maximum and minimum gain setting, respectively.