S. Siskos

GaAs/(Ca,Sr)F2/(001) GaAs lattice‐matched structures grown by molecular beam epitaxy

Epitaxial growth of GaAs/(Ca, Sr) F2/GaAs structures by means of molecular beam epitaxy has been demonstrated. It has been shown that it was possible to grow layers with good crystalline quality and no noticeable interdiffusion at the interfaces. In addition, the uppermost GaAs layers present interesting electrical properties, exhibiting electron Hall mobilities of about 1300 cm2/Vs.

Epitaxial growth of lattice‐matched CaxSr1−xF2 on (100) and (110) GaAs substrates

Epitaxial growth of monocrystalline layers of mixed fluorides (CaxSr1−xF2) using molecular beams on GaAs substrates is reported for the first time. Good morphology and crystalline quality of the layers have been obtained. Some possible applications of these structures are considered, and preliminary results are reported concerning the electrical behavior of metal‐insulator‐semiconductor devices and the use of CaxSr1−xF2 as encapsulant or as masking material for GaAs.

Differential-voltage attenuator based on floating-gate MOS transistors and its applications

In this brief, a very simple differential voltage attenuator based on floating-gate MOS transistors (FGMOS) is proposed. The attenuator constructed by only two stacked identical FGMOS in saturation region, provides a voltage output proportional to the difference of the two input voltages. The advantages of this attenuator are the low supply operation, the rail-to-rail input range with small linearity error and the single-ended input processing. A very efficient technique to transform any circuit that requires only balanced inputs into the single-ended counterpart based on the attenuator, is proposed. Using this technique, a number of single-ended computational circuits are produced such as voltage squarer, four-quadrant multiplier, and vector summation circuit. The circuits can be fabricated in standard double-poly, double-metal CMOS technology and they are suitable for analogue signal processing and neural networks applications. SPICE simulation results using 2-/spl mu/m MIETEC CMOS process parameters demonstrate the feasibility and the accuracy of the circuits.

Analog implementation of fast min/max filtering

An analog implementation of running min/max filters based on current-mode techniques is presented. Switched-current delay cells and current/voltage two inputs min/max selectors are used either for current or voltage inputs respectively. The voltage two input min/max circuit is designed using current conveyors and a modified structure of this is used to implement the running min/max filter for window size n=8. Simulation results demonstrate the feasibility of the proposed implementation, which can be extended to a higher window size.

Design of voltage-mode and current-mode computational circuits using floating-gate MOS transistors

In this paper, we present voltage-mode and current-mode computational circuits using floating-gate MOS (FGMOS) transistors, operating in saturation region. The circuits are designed using two FGMOS basic-cells, each one formed by three floating-gate transistors with common source. The first basic cell is connected in voltage mode, while the second one is connected in current-mode configuration in order to implement voltage and current-mode circuits, respectively. Using the basic FGMOS cells, voltage and current squarers, four-quadrant multipliers and a current square rooter are designed. Mismatches and distortion analysis for the proposed circuits have been elaborated. The most important advantages are, rail-to-rail dynamic input range, low distortion and ability for either differential or single-ended input signals. Simulation results demonstrate the feasibility and the accuracy of the circuits.

Design and applications of an easily integrable CMOS operational floating amplifier for the megahertz range

The design and major applications of a general purpose current mode building block are presented in this paper. This circuit is basically a high gain transconductance scheme with differential current output terminals previously termed operational floating amplifier (OFA). The novel structure proposed here is shown to implement a very flexible and high performance amplifier which can be used in almost all applications employing conveyors, current feedback amplifiers or even conventional operational amplifiers with improved performance characteristics. This presentation is also supported by experimental measurements on a prototype circuit realized in CMOS technology.

Advanced Low-Noise X-Ray Readout ASIC for Radiation Sensor Interfaces

A VLSI readout front-end architecture, dedicated for X-ray imaging, using specific capacitive silicon detectors, with capacitance ranging from 2 to 10 pF, is described. Critical design issues such as the noise optimization and the shaper implementation technique are addressed and the first performance - test results of a fabricated prototype in a 0.35-mum 3.3-V CMOS process, are presented. Important feature of the design is the novel CR - RC2 pulse-shaper configuration since in this section, transconductor circuits are used in order to provide a broad range of continuous variable peaking time, programmable gain and adjustable undershoot while still maintaining the noise performance and the required linearity of the specific radiation detection application. Regarding the readout ASIC performance characteristics, the power consumption is 1 mW per channel, the equivalent noise charge at 1.81-mus peaking time is 382 e- plus 21 e- per picofrard of detector capacitance. The topology achieves a conversion gain equal to 3.31 mV/fC and a linearity of 0.69%.

A simple and continuous polycrystalline silicon thin-film transistor model for SPICE implementation

A simple current-voltage model for polycrystalline silicon thin-film transistors (polysilicon TFTs) is proposed, including the sixth-order polynomial function coefficients fitted to the effective mobility versus gate voltage data, the channel length modulation, and impact ionization effects. The model possesses continuity of current in the transfer characteristics from weak to strong inversion and in the output characteristics throughout the linear and saturation regions of operation. The model parameters are used as input parameters in AIM-SPICE circuit simulator for device modeling. The model has been applied in a number of long and short channel TFTs, and the statistical distributions of the model parameters have been derived which are useful for checking the functionality of TFTs circuits with AIM-SPICE.

Noise optimised charge-sensitive CMOS amplifier for capacitive radiation detectors

A low-voltage, low-noise, charge-sensitive preamplifier (CSA) for particle tracking using a silicon strip detector was designed. The preamplifier was optimised in terms of the total output noise performance using a noise minimisation technique based on the MOSFET noise small signal equivalent circuit and readout front-end noise optimisation criteria valid in the strong inversion region. The preamplifier was designed and fabricated in a 0.35 m CMOS process by Austria Mikro Systeme for a specific silicon strip detector of 2 pF capacitance for X-ray spectroscopy. The circuit exhibits satisfactory performance compatible to the specific low-energy radiation detection application. Particularly, the CSA provides an equivalent noise charge of 254 e + 13.5+e - /pF, consumes 165 muW and achieves an output conversion gain equal to 2.81 mV/fC and a linearity <0.57 . Analysis is supported by extensive measurement results confirming the circuit characteristics and their flexibility to be used in a variety of readout applications.

Current-mode non-linear building blocks based on floating-gate transistors

Simple current-mode non-linear computational circuits based on a basic cell built with floating-gate MOS transistors are proposed. The basic cell is used to construct a current square-root circuit, a current squarer and a four-quadrant current multiplier. The circuits offer large input range, low harmonic distortion and high linearity. Spice simulation results verify the performance of the proposed circuits.