Grzegorz Blakiewicz

An Analog Sub-Miliwatt CMOS Image Sensor With Pixel-Level Convolution Processing

A new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3 × 3 kernel. The proof-of-concept circuit is implemented in 0.35 μm CMOS technology, and contains a 64 × 64 SIMD matrix with embedded APEs. The matrix dissipates less than 0.3 mW (less than 0.1 W per APE) of power under 3.3 V supply, and its image processing speed is up to 100 frames/s.

Output-capacitorless low-dropout regulator using a cascoded flipped voltage follower

An improved flipped voltage follower (FVF) and its application to a low-dropout (LDO) voltage regulator are presented. The proposed FVF improves most weaknesses of the classical one, namely its poor time response to the output current change from low to high value and poor stability for large capacitive load. The most important parameters of the modified FVF are analysed and described by analytical expressions. The parameters of the classical FVF and the improved one are compared and discussed. LDO regulator using the improved FVF is designed and implemented in AMS CMOS 0.35 m technology. The measurement results of a test circuit show its relatively high current efficiency of 74 and 99.93 for output current 100 μA and 50 mA, respectively. The output voltage overshoot and undershoot are below 46 and 75 mV for output current change from 0.1 to 50 mA with the rise and fall times equal to 0.3 s, and load capacitance 0 100 pF.

Frequency compensation for two-stage operational amplifiers with improved power supply rejection ratio characteristic

A frequency compensation technique improving characteristic of power supply rejection ratio (PSRR) for two-stage operational amplifiers is presented. This technique is applicable to most known two-stage amplifier configurations. The detailed small-signal analysis of an exemplary amplifier with the proposed compensation and a comparison to its basic version reveal several benefits of the technique which can be effectively exploited in continuous-time filter designs. This comparison shows the possibility of PSRR bandwidth broadening of more than a decade, significant reduction of chip area, the unity-gain bandwidth and power consumption improvement. These benefits are gained at the cost of a non-monotonic phase characteristic of the open-loop differential voltage gain and limitation of a close-loop voltage gain. A prototype-integrated circuit, fabricated based on 0.35 μm complementary metal-oxide semiconductor technology, was used for the technique verification. Two pairs of amplifiers with the classical Miller compensation and a cascoded input stage were measured and compared to their improved counterparts. The measurement data fully confirm the theoretically predicted advantages of the proposed compensation technique.

Analog CMOS processor for early vision processing with highly reduced power consumption

A new approach to an analog ultra-low power vision chip design is presented. The prototype chip performs low-level convolutional image processing algorithms in real time. The circuit is implemented in 0.35 µm CMOS technology, contains 64 × 64 SIMD matrix with embedded analogue processors APE (Analogue Processing Element). The photo-sensitive-matrix is of 2.2 µm × 2.2 µm size, giving the density of 877 processors per mm2. The matrix dissipates less than 0.4 mW (less than 0.1 µW per processor) of power under 3.3 V supply, and their image processing speed is up to 100 frames/s.

Estimation of supply current spectrum for early noise evaluation

An analytical method for power supply spectrum estimation to be used in early system planning is proposed. The method is based on a careful evaluation of a number of parameters of an equivalent inverter; rise time, fall time and widths of current impulses. We assume an inverter to be a basic building component of digital blocks. Using the proposed method one can determine estimates of power supply noise levels and characteristic frequencies in its spectrum

Supply current spectrum estimation of digital cores at early design

A new, approximate method is presented to calculate a digital core supply current spectrum. The method is based on characterisation of supply current pulses in terms of the rise and fall times and pulse width. The upper limits (an envelope) for the supply current spectrum are derived using logic signal transition densities at digital core internal nodes. Contrary to the known methods, the proposed one uses limited data and generates much needed supply current information strongly desired by a system designer at a very early system planning. By using the probabilistic and statistical techniques the method is only weakly dependent on input sequence pattern and gives reliable final results.

Active Suppression of Substrate Noise in CMOS Integrated Circuits

Noise generated by digital sub-circuits becomes serious problem in fast mixed signal systems on chip (SoC). Digitally generated noise corrupts supply voltages and is propagated inside a silicon substrate as so called substrate noise. A discussion and simplified analysis of passive and active circuits for substrate noise suppression is presented in this paper. An example of an active circuit is design and tested by means of simulations. The achieved results show higher efficiency of the active circuits in substrate noise attenuation in comparison to known passive solutions.

Optimization of active circuits for substrate noise suppression

Noise generated by digital sub-circuits becomes a serious problem in fast mixed signal system on chips (SoCs). Digitally generated noise corrupts supply voltages and is propagated inside a silicon substrate as so called substrate noise. The circuits for substrate noise suppression proposed so far have serious weaknesses due to their frequency limitations. We present a method for optimization of noise-suppressive active circuits to improve their properties at high frequencies, illustrate efficiency of the optimization procedure an example of an active circuit consisting of a single voltage gain stage and a buffer is designed and tested by means of simulations. The improved circuits show over 9 dB better substrate noise attenuation at frequencies above 1 GHz in comparison to known passive and active solutions.

Noise Modeling Of Static Cmos Gates For Low-noise Circuit Synthesis

This paper presents an efficient method for supply-current spectrum estimation for the static CMOS family of digital gates. It extends the previous approach (Blackiewicz, 2006), that considered only the noise due to a gate output switching, by including the noise generated by glitching, and short impulses. Estimation of digital circuit noise is used in early design planning of modern mixed-signal system-on-chips (MS-SoCs), composed of sensitive analogue and usually noisy digital blocks, to reduce substrate coupling-noise in analogue blocks through proper floorplan design (Blackiewicz, 2005)

Modeling of substrate noise block properties for early prediction

We propose a new approach to substrate noise modeling in early design planning of mixed-signal systems-on-chips (MS-SOCs). It can be applied to a system without any detailed knowledge (physical-layout) about its building blocks. We assume and justify that, in early prediction, only the most significant noise sources of substrate noise need to be considered. To capture important properties of substrate noise we consider the frequency-dependent sensitivity of analog blocks and a noise injection model for noisy digital blocks. We use experimental substrate noise simulations to build our models, and give suggestions on how to estimate noise parameters for building blocks of MS-SOC.