Jacek Jakusz

An Analog Sub-Miliwatt CMOS Image Sensor With Pixel-Level Convolution Processing

A new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3 × 3 kernel. The proof-of-concept circuit is implemented in 0.35 μm CMOS technology, and contains a 64 × 64 SIMD matrix with embedded APEs. The matrix dissipates less than 0.3 mW (less than 0.1 W per APE) of power under 3.3 V supply, and its image processing speed is up to 100 frames/s.

A linear CMOS OTA for VHF applications

The design of a linear, fully-balanced, voltage-tunable CMOS operational transconductance amplifier (OTA) with improved gain and very wide bandwidth is described. It uses a cross-coupled, two-differential-pair transconductor together with a negative resistance load for compensating the parasitic output resistance of the OTA. Since no additional internal nodes are generated DC-gain enhancement is obtained without any bandwidth limitation. SPICE simulation results show THD<1% at 1.9 V/sub p-p/ with dynamic range equal to 63 dB at a power consumption of 2.7 mW from a single 5-V supply. Application to a lowpass filter in the VHF range is presented as an example, assuming implementation in a standard 2 /spl mu/m CMOS process (MOSIS). The cutoff frequency of the filter is tunable in the range of 8.3-50.0 MHz.

Analog CMOS processor for early vision processing with highly reduced power consumption

A new approach to an analog ultra-low power vision chip design is presented. The prototype chip performs low-level convolutional image processing algorithms in real time. The circuit is implemented in 0.35 µm CMOS technology, contains 64 × 64 SIMD matrix with embedded analogue processors APE (Analogue Processing Element). The photo-sensitive-matrix is of 2.2 µm × 2.2 µm size, giving the density of 877 processors per mm2. The matrix dissipates less than 0.4 mW (less than 0.1 µW per processor) of power under 3.3 V supply, and their image processing speed is up to 100 frames/s.

Niskomocowy komparator z zatrzaskiem przeznaczony do cyfrowego przetwornika obrazu CMOS

W artykule zaproponowano realizacje analogowego niskomocowego komparatora z zatrzaskiem przeznaczonego do cyfrowego piksela CMOS. Komparator zaprojektowano w technologii 0,35 μm CMOS. Uklad zoptymalizowano pod kątem obnizenia poboru mocy ze źrodla zasilającego i powierzchni topografii. W projekcie zastosowano techniki redukcji poboru mocy statycznej i dynamicznej. Komparator przebadano symulacyjnie w ukladzie cyfrowego piksela z przetwornikiem A/C typu single-slope. Uklad zasilany napieciem 3,3 V pobiera moc 1,8 μW przy zalozeniu 100 tysiecy cykli konwersji A/C na sekunde i zajmuje powierzchnie 220 μm^2.