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Stefan Gruss

Infineon Technologies

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Publication

Featured researches published by Stefan Gruss.

Metrology, Inspection, and Process Control for Microlithography XVIII | 2004

Test of a new sub-90-nm DR overlay mark for DRAM production

Stefan Gruss; Ansgar Teipel; Carsten Fuelber; Elyakim Kassel; Mike Adel; Mark Ghinovker; Pavel Izikson

An improved overlay mark design was applied in high end semiconductor manufacturing to increase the total overlay measurement accuracy with respect to the standard box-in-box target. A comprehensive study has been conducted on the basis of selected front-end and back-end DRAM layers (short loop) to characterize contributors to overlay error. This analysis is necessary to keep within shrinking overlay budget requirements.

Archive | 2004

Method for fabricating a contact hole plane in a memory module

Hans-Georg Fröhlich; Oliver Genz; Werner Graf; Stefan Gruss; Matthias Handke; Percy Heger; Lars Heineck; Antje Laessig; Alexander Reb; Kristin Schupke; Momtchil Stavrev; Mirko Vogt

Archive | 2004

Method for reducing an overlay error and measurement mark for carrying out the same

Stefan Gruss; Detlef Hofmann; Rainer Pforr; Mario Hennig; Guido Thielscher; Hans-Georg Froehlich

Archive | 2004

Method for detecting positioning errors of circuit patterns during the transfer by means of a mask into layers of a substrate of a semiconductor wafer

Lothar Bauch; Stefan Gruss; Ansgar Teipel; Hans-Georg Froehlich

Archive | 2005

Aligning semiconductor wafer using adjustment marks, adds two spaced structural components joined by trench, with sidewalls still detectable after subsequent processing

Heike Drummer; Jens Stäcker; Hans-Georg Froehlich; Stefan Gruss; Ralph Wienhold; Werner Graf

Archive | 2005

Detecting wafer scanner translation fault in photo-lithographic structuring of semiconductor wafer, especially with RAM component, by forming overlay targets in illumination fields and detemining displacement

Stefan Gruss; Manuel Vorwerk; Hans-Georg Froehlich; Raphael Ehrbrecht

Archive | 2005

Overlay measurement structure method e.g. for determining relative off set of two structure switch patters on semiconductor wafer via raster electron microscope

Ansgar Teipel; Stefan Gruss; Hans-Georg Froehlich

Archive | 2005

Verfahren zur Reduzierung eines Überdeckungsfehlers sowie Meßmarke zur Durchführung des Verfahrens

Detlef Hofmann; Mario Hennig; Guido Thielscher; Stefan Gruss; Rainer Pforr; Hans-Georg Froehlich

Archive | 2003

Verfahren zur Reduzierung eines Überdeckungsfehlers A method for reducing an overlay error

Hans-Georg Froehlich; Stefan Gruss; Mario Hennig; Hofmann Detlef; Pforr Rainer; Guido Thielscher

Archive | 2003

Verfahren zur Bestimmung eines Translationsfehlers eines Waferscanners bei der photolithographischen Strukturierung eines Halbleiterwafers A method for determining a translation error of a wafer scanner with the photolithographic patterning of a semiconductor wafer

Raphael Ehrbrecht; Hans-Georg Froehlich; Stefan Gruss; Manuel Vorwerk

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Hans-Georg Froehlich

Infineon Technologies

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Ansgar Teipel

Infineon Technologies

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Guido Thielscher

Infineon Technologies

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Mario Hennig

Qimonda

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Detlef Hofmann

Infineon Technologies

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Lothar Bauch

Infineon Technologies

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Rainer Pforr

Infineon Technologies

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Werner Graf

Infineon Technologies

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Hans-Georg Fröhlich

Infineon Technologies

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Heike Drummer

Infineon Technologies

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