Werner Graf

Word line to bit line spacing method and apparatus

Method for production of contacts on a wafer

Interconnect structure for semiconductor devices

Phosphorous doped SOG as a pre-metal-dielectric for sub-50nm technology nodes

Method for forming an integrated circuit having an active semiconductor device and integrated circuit

Integrated circuit for use in e.g. electronic system, has interface-structures directly connected to doped area in respective partial areas of contact surface, where structures are made from respective conducting materials

Integrated circuit e.g. semiconductor memory device, manufacturing method, involves etching trench in substrate in active region such that trench structure defines dimension of trench in lateral direction, and active device formed in trench

Integrated Circuit with a Contact Structure Including a Portion Arranged in a Cavity of a Semiconductor Structure

The integration of alternative contact cleaning techniques for future DRAM technology nodes

Herstellungsverfahren für eine Halbleiterstruktur Manufacturing method of a semiconductor structure