Niklas Zimmermann

Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GPS/Galileo Low-If Receiver

In this paper, starting from theoretical considerations on the chosen architecture, chip design and measurement results are presented for a continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulator for a combined GPS and Galileo low-IF receiver. The modulator chip was designed in a standard 0.25 mum CMOS technology. The designed CT quadrature bandpass SigmaDelta modulator has a power consumption of 20.5 mW with 1.8-V supply voltage, a dynamic range of 57.5 dB and 50.2 dB and a peak SNDR of 52.9 dB and 48.4 dB for GPS/Galileo, respectively. The core area of the chip is 0.37 times 0.54 mm2.

System architecture of an RF-DAC based multistandard transmitter

In this paper the system concept of a radiofrequency digital-to-analog converter (RF-DAC) based multistandard transmitter is presented. The RF-DAC combines DA converter and up-conversion mixer in a single building block. Thereby, the analog baseband blocks are eliminated and replaced by easily reconfigurable digital blocks. Requirements on the digital and mixed-signal blocks are discussed. Spurious emissions are a major issue of this ‘direct digital modulator’. This is especially true for multiradio devices with several receivers running simultaneously and in close proximity to the transmitter. Therefore, a maximum emission limit is formulated and especially critical frequency bands are identified. Several techniques for reducing the spurious emissions are discussed and performance requirements for an LTE transmitter and its main building block are found. System simulations demonstrate the feasibility of the concept.

System architecture of an all-digital GHz transmitter using pulse-width/position-modulation for switching-mode PAs

This paper presents a novel concept for direct-pulse-width/position-modulation (PWPM) in an all-digital transmitter by using a parallel baseband PWPM and high speed digital up-conversion. By parallel calculation and subsequent serialization of the digital PWPM signal carrier frequencies above 1 GHz become feasible. PWPM enables the usage of highly efficient switching-mode power amplifiers (SMPA) and direct control of the output power. Because PWPM modulator can be completely implemented in the digital, time discrete domain, all analogue baseband blocks can be dropped and replaced by reconfigurable digital blocks. The only remaining mixed-signal and analogue blocks are the multiplexer and the power amplifier. Requirements on the digital and mixed-signal blocks are discussed. Feasibility of the concept is demonstrated by system and circuit simulations showing the possibility of using digital PWPM in wireless applications.

An RFDAC based reconfigurable multistandard transmitter in 65 nm CMOS

This paper presents an RFDAC based transmitter for wireless mobile and connectivity applications in a 65 nm CMOS technology. The transmitter RFDAC has a segmented architecture employing 4 LSB and 16 MSB unit cells for each I and Q path, thus providing a resolution of 8 bit + signum. Switchable LO drivers and unit cells with current shutdown are used to reduce power dissipation when transmitting signals with high PAPR such as IEEE 802.11 (WLAN) or 3GPP Long Term Evolution (LTE). The frontend is capable of transmitting an 64 QAM-OFDM WLAN signal at a center frequency of 1 GHz with an output power of -8 dBm and an EVM of 4.66 %. Analog power dissipation is 34 mW, clock and LO divider use less than 10 mW, and the digital block consumes about 87 mW. The area of the frontend is about 0.4 mm2.

Design of an RF-DAC in 65nm CMOS for multistandard, multimode transmitters

This work presents a radiofrequency digital-to-analog converter (RF-DAC) in 65nm CMOS. The RF-DAC combines DAC and mixer functionality in a single building block. It is the basis for a ‘direct-digital’ vector modulator used in reconfigurable broadband multistandard transmitters for mobile communications. After introducing the basic idea of the RF-DAC, an appropriate transmitter architecture is discussed. Subsequently, a novel RF-DAC circuit implementation based on a Sooch cascode current mirror is presented. The design is optimized for high output power and high efficiency over a broad output power range. Based on the RF-DAC a vector modulator architecture is developed. Simulation results show the feasibility of the concept.

Power amplifiers in 0.13 μm CMOS for DECT: a comparison between two different architectures

Two 1.9 GHz power amplifiers (PAs) have been designed and fabricated in a 0.13 μm standard CMOS process. They are both two-stage push-pull amplifiers with more than 27dBm output power. The amplifier stages of both PAs have exactly the same transistor structures and sizes, but the input and interstage matching networks are realized differently. The first PA uses on-chip transformers for the coupling of the stages, the second PA LC matching networks. In this paper both topologies are compared and benefits and drawbacks of the different structures are discussed.

A comparison of bandwidth setting concepts for Q-enhanced LC-tanks in deep-sub micron CMOS processes

In this paper LC-resonator bandwidth setting techniques in deep-sub micron CMOS processes are examined and compared with the main focus on Q-enhancement, linearity, noise, power consumption and controllability at low supply voltages. Simulations have been performed using an ideal amplifier model to achieve results independent of the purpose of the circuit. The Q-enhancement is achieved by positive feedback into the gates of a cross coupled MOSFET transistor pair. The different Q-tuning concepts include current control techniques as well as capacitive subdivision in the feedback path. As result of this work, a combination of tail current controlled and capacitive subdivision has been found to be the best mean to achieve highest linearity at good controllability. Simulation results show that a quality factor around 100 is possible at a current consumption of maximum 3 mA. The equivalent input noise does not exceed 1.5 nV/radic(Hz) with total harmonic distortion around 0.005% which makes the circuit reasonable for application in LNAs as well as for transmitter structures.

Optimized mismatch shaping for an RF-DAC based OFDM transmitter

This work presents an element selection logic (ESL) for a radio frequency digital to analog converter (RF-DAC) based multistandard transmitter in 65 nm CMOS. After introducing the transmitter system and the basics of mismatch shaping, the ESL is applied to an OFDM transmitter. The design is optimized with respect to the signal properties and synthesis is done for the mentioned CMOS technology. Simulation results show a significant improvement of the signal quality in the desired band.

A low mismatch symmetric charge pump for the application in PLLs

This paper proposes a charge pump with a symmetric structure that minimizes mismatch between charge and discharge currents and phase offset. The origins and influences of charge pump mismatch are discussed and theoretically analyzed. Subsequently the simulation results of the proposed charge pump are compared with conventional structures to show its benefits.

An over-voltage protection circuit for CMOS power amplifiers

With increasing demand for higher integration and lower cost of mobile communication devices there is a growing trend towards the use of CMOS power amplifiers (PAs) instead of GaAs or SiGe PAs. Although being comparatively inexpensive, CMOS not only suffers from inferior RF performance but also from low breakdown voltages. This gets an issue especially for the PA output stage, when load mismatches lead to high voltage-standing wave ratios (VSWR) and therefore high peak voltages at the PA output. In this work a 27 dBm PA in 0.13 mum CMOS with an integrated VSWR protection circuit is presented. A control loop detects critically high voltage amplitudes at the PA output and reduces the PA gain in order to lower the output voltage swing to uncritical values.