Song-Bok Kim

A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25

Quadrature bandpass SigmaDelta modulators based on polyphase filters are suited for analog-to-digital conversion in GSM/EDGE low-IF receivers. This paper presents a continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulator with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology - which is a desirable solution for implementation in low power applications. A new compensation scheme for the polyphase filter is proposed. The summation of feedforward signals is implemented by weighted capacitors, without the necessity of any additional active components. The effectiveness of the proposed architecture is proved on a test chip which was designed in a standard 0.25 mum CMOS technology. The designed SigmaDelta modulator has a power consumption of 2.7 mW at 1.8 V supply voltage, a dynamic range of 90.3 dB and a peak SNDR of 86.8 dB. The chip area is 0.5 times 1.4 mm2 including pads.

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In this paper, starting from theoretical considerations on the chosen architecture, chip design and measurement results are presented for a continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulator for a combined GPS and Galileo low-IF receiver. The modulator chip was designed in a standard 0.25 mum CMOS technology. The designed CT quadrature bandpass SigmaDelta modulator has a power consumption of 20.5 mW with 1.8-V supply voltage, a dynamic range of 57.5 dB and 50.2 dB and a peak SNDR of 52.9 dB and 48.4 dB for GPS/Galileo, respectively. The core area of the chip is 0.37 times 0.54 mm2.

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This paper presents a strategy for successful polyphase-filter design for continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulators. Based on a low-pass filter with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology - which is suited for implementation in low-power applications - analytical equations are derived. A new compensation scheme is proposed and implemented by cross-coupling additional resistors, without the necessity of extra-active components. Translation to intermediate frequency in second- and fourth-order polyphase filters with the proposed compensation scheme are compared to analytical considerations and simulation. Nonlinearities introduced by mismatch of feedforward coefficients and finite gain-bandwidth of amplifiers are considered.

Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GPS/Galileo Low-If Receiver

This paper describes an extension to the popular Matlab delta-sigma toolbox. The delta-sigma toolbox is restricted to the generation and simulation of low-pass DeltaSigma analog to digital converters (ADCs). This work enables the toolbox to generate and simulate quadrature bandpass (polyphase) ADCs. After a short introduction and general explanations of DeltaSigma based ADCs, the generation of optimized polyphase loop filters from their lowpass equivalents using the toolbox approach is described. The corresponding sourcecodes for generation and simulations of these ADCs are provided. Demonstration examples with various simulation results are supplied. The toolbox enhancements have been published for download at the Mathworks Matlab internet site.

A Polyphase Filter Design for Continuous-Time Quadrature Bandpass Sigma–Delta Modulators

Continuous-time (CT) SigmaDelta modulators seriously suffer from excess loop delay, which can not be seen in discrete-time designs. In this paper, it is shown that excess loop delay decreases the signal-to-noise ratio (SNR), input dynamic range (DR) and stability in CT complex SigmaDelta modulator with CIFF topology. A method for its compensation is presented. The proposed compensation scheme has a unity delay in front of the quantizer and complex compensation coefficients which are determined by analysis of the ideal DT loop filter transfer function. The simulation results are compared to analytical considerations.

Simulation of quadrature-bandpass Sigma-Delta analog to digital converters using state space descriptions

This paper presents a continuous-time quadrature bandpass sigma-delta (SigmaDelta) modulator with a chain of integrators with weighted capacitive feedforward summation (CICFF) topology-which is suited for implementation in low power applications. A new compensation scheme for a polyphase filter is proposed. The summation of feedforward signals is implemented by weighted capacitors, without the necessity of any additional active components. The effectiveness of the proposed architecture is proved on a test chip which was designed in a standard 0.25-mum CMOS technology. The designed SigmaDelta modulator has a power consumption of 2.7 mW at 1.8 V supply voltage, a dynamic range of 90.3 dB and a SNDR of 86.8 dB. The chip is 0.5 times 1.4 mm2 including pads.

A compensation method of the excess loop delay in continuous-time complex sigma-delta modulators

Continuous-time (CT) complex SigmaDelta modulators seriously suffer from delay in real and imaginary feedback paths. The mismatched loop delay results in a degradation of the signal-to-noise ratio. In this paper, analytical considerations of mismatched loop delay in CT complex SigmaDelta modulators are presented. Discrete-time equivalent transfer functions to that of a CT complex loop filter are derived from continuous-discrete transformation in the complex signal domain. A solution for reducing or compensating the effect of mismatched loop delay is proposed.

Continuous-time quadrature bandpass sigma-delta modulator with capacitive feedforward summation for GSM/EDGE low-IF receiver

Continuous-time quadrature bandpass sigma-delta modulators seriously suffer from finite gain bandwidth of the amplifiers they contain. In this paper, the performance limitation of the continuous-time quadrature bandpass sigma-delta modulator caused by finite gain bandwidth is presented. Finite gain bandwidth results in an unstable behavior of the complex integrators and a deviation from the center frequency. In order to improve stability of the complex integrator by finite GBW, it is desirable to employ a lossy integrator. The deviation from the center freqency affects the in-band noise power of the modulator. A compensation solution for reducing the deviation from the center frequency is proposed by means of transconductors at the amplifier inputs.

Effect of Mismatched Loop Delay in Continuous-Time Complex Sigma-Delta Modulators

A multi-bit sigma-delta (SigmaDelta) modulator is an attractive solution for a high-resolution analog-to-digital conversion. In multi-bit complex SigmaDelta modulators, the overall resolution of the modulator is limited by the mismatch errors in the digital-to-analog converters (DACs) of the I/Q-paths. The mismatch in the DAC bank causes unwanted additional noise power in passband. In this paper, a first-order complex mismatch shaper, which is based on a complex noise shaping technique, is presented for the reduction of a mismatch effect in the feedback multi-bit DACs of the complex SigmaDelta modulator. From the purpose of mismatch shaping, the complex mismatch shaper should have the same intermediate frequency as the modulator. The proposed complex mismatch shaper can be applied to the tree-structured element selection logic (ESL). Finally, the effectiveness of the proposed mismatch shaper is proved by simulation.

Performance limitation by finite gbw in continuous-time quadrature bandpass sigma-delta modulators

In this paper, the jitter-induced noise is estimated in continuous-time quadrature bandpass sigma-delta modulator. The closedform formulas for the output spectrum of noise caused by clock jitter are derived. The correctness of the obtained analytical results is proved, based on model simulation. The noise introduced by clock jitter increases the in-band noise power, and therefore decreases the signal-to-noises ratio (SNR). The jitter-induced noise power depends on the noise shaping transfer function and the input signal level. The formers optimization gives improvement in the SNR. The dependence on the latter introduces the non-linearity of the modulator.