Stefano Oggioni

Polymer-Waveguide-Based Board-Level Optical Interconnect Technology for Datacom Applications

On the basis of a realized 12times10 Gb/s card-to-card optical link demonstrator, the capabilities of a polymer-waveguide-based board-level optical interconnect technology are presented. The conception and realization of the modular building blocks required for this board-level optical interconnect technology are described in detail. In particular, we report on the fabrication and characterization of board-integrated optical low-loss polymer waveguides that are compatible with printed circuit board (PCB) manufacturing processes. We also explain our fully passive alignment technique, superseding time-consuming active positioning of components and connectors. To realize optical transceiver modules comprising vertical cavity surface emitting laser (VCSEL) arrays with laser drivers and photodetector arrays with transimpedance amplifiers (TIAs), a mass-production concept based on wafer-level processing has been elaborated and successfully implemented.

Investigation of novel solder patterns for power delivery and heat removal support

An innovative approach for electrical chip to substrate and chip to chip interconnects is proposed. The coexistence of solder balls and rails on a chip is discussed, supporting power delivery and heat removal for high-performance flip-chip-onboard and 3D stack applications. The concept enables further bandwidth and current density scaling at a high count of interconnects for signaling, but also at a high solder area fill factor for power delivery and heat removal. The rail-shaped solder joints are also compatible with the current floorplans of microprocessors with voltages arranged in lines. After reflow, solder rails compared to balls can result in a much larger maximal solder width relative to their pads. Therefore, a staggered array arrangement was proposed to minimize shorting risk. In addition, a solder height engineering strategy utilizing modulated pad shapes is discussed to yield equal solder heights for balls and rails present on the same device. However, improper rail design was found to lead to two instability types: 1) Balling and 2) Asymmetric Solder Accumulation. The first is the result of a solder height to width ratio of larger than approximately 0.6 considering long rail lines. The second occurs due to fabrication imperfections. The initial non-symmetric pad/solder shape can cause the accumulation of solder at one rail end (typically the end with the larger area) after reflow. The stability of Bow Tie Rails against Asymmetric Solder Accumulation was investigated to provide design rules for a robust rail design. Accordingly, a solder shape phase diagram indicating the parameters of the three identified phases is compiled. Experimental investigations of reflown solder shapes were complemented with numerical results using a surface energy minimization tool called Surface Evolver. A prediction quality of better than 9% was identified indicating the applicability of the tool to perform solder shape designs. The solver was also capable to predict the mentioned instabilities, rendering the tool even more valuable. Finally, a thermal interface resistance benchmark of ball and rail-like interconnects is performed in a bulk thermal tester. The rail interface with a solder fill factor of 57% yielded a 7 times reduced interface resistance.

Thermal power plane enabling dual-side electrical interconnects for high-performance chip stacks: Implementation

We report on the design, implementation and performance of a laminate named Thermal Power Plane and solder joints that enable dual-side electrical interconnects (EIC) to a chip stack. This novel packaging topology with a laminate on both sides of the chip stack doubles the number of EIC thus supporting increased communication bandwidth and power density. In addition, in a two-die stack, all power TSVs can be eliminated with the advantage of gained silicon active area. The use of two laminates also enables individual test & burn-in of the dies before stack formation. The TPP needs to provide efficient heat removal and current feed in the out-of-plane and in-plane direction, respectively. An 8+1 coreless build-up laminate with aligned and stacked thermal laminate vias (TLVs) was designed and implemented. Bar-, chevron- and mesh-like copper planes with varying TLV densities were characterized. The mesh design resulted in minimal warpage and voltage drop. The bar and chevron designs result in the lowest thermal resistance. In combination with rail-shaped solder interconnects interfacing between TPP and top chip, the overall thermal resistance of the junction to cold plate of the dual-side EIC approach can outperform that of the standard single-side EIC package. The electrical DC characteristics of the TPP was also evaluated experimentally. The sheet resistance of 0.21 MΩ allows the supply of the required currents within the voltage uniformity requirements. In general, the experimental evaluation supports the feasibility of the proposed dual-side EIC concept supporting further performance and efficiency scaling of high-performance chip stacks.

Integration of optical I/O with organic chip packages

With the ongoing progress in chip scaling, the data flow to and from chip packages is increasing accordingly. The simultaneous increase of channel count and channel speed in an essentially constant form factor becomes a more and more demanding challenge. The resulting I/O-bottleneck is considered to be a major limiting factor for the overall performance of future chip packages and computing systems. Optical interconnects offer both increased channel density as well as longer link reach at high frequencies. Our current work focuses on integrating optical I/O with standard organic packages in order to maximize the aggregate data flow to and from such packages. We present a novel approach for attaching an electro-optical conversion module directly on top of the organic chip package, together with experimental results of a first prototype implementation.

Embedded power insert enabling dual-side cooling of microprocessors

A dual-side cooling topology is proposed that is achieved by embedding a power insert into the organic substrate of a chip or chip stack. The power insert consists of vertical copper lamellas supporting lateral current feed in addition to vertical heat dissipation at minimal electrical and thermal gradients. The lateral current feed capability is key to enable the introduction of the cold plate on the bottom side of the substrate. Thermal and electrical finite-element modeling was performed to determine the optimal pitch of the power insert lamella of 270 μm and 350 μm to obtain a total thermal resistance of 21 K-mm2/W and a voltage drop of 2 mV, respectively. The 10 × 10 mm2 power inserts are fabrication by means of a copper and prepreg lamination process, followed by a sawing and polishing singulation step. The embedding of the power insert is described, considering additional redistribution layers to accommodate also smaller interconnect pitches on the chip side. The effective thermal conductivity of the power insert was derived by bulk-thermal measurement and yielded 320±50 W/m-K, ten times the performance of state-of-the-art substrates with thermal via arrays. Finally, we demonstrate the benefits of the dual-side cooling approach in a thermal benchmark study that compares it with back- and front-side cooling. Dual-side cooling not only halfs the total thermal resistance, but also enables the integration of pyramid-like chip stacks and the placement of high-power dies in the bottom tiers of a stack.

Optical Transceiver Module for 1.2 Tb/s Based on Flexible Circuit Technology

We present a versatile electro-optical packaging platform for optical transceiver modules suitable for very high aggregate I/O capacity, as required, for example, in (disaggregated) datacenters and servers. Real-estate limitations on the board or on the processor package laminate are overcome by using a flexible printed circuit board substrate that is folded around a solid body, resulting in a 3-D package assembly. A 48

Thermal power plane enabling dual-side electrical interconnects for high-performance chip stacks: Concept

\text {Gb/s} \times 10

Ball grid array module

Gb/s transceiver prototype is demonstrated as well as the design path toward a transceiver with 1.2-Tb/s aggregate I/O bandwidth. Accounting for large-scale manufacturing and deployment, we explicitly address the requirements of the optical, mechanical, thermal, and electrical interfaces as well as of all associated manufacturing processes.

Electronic package with enhanced pad design

In this paper, a novel concept of dual-side electrical interconnects (EIC) to a chip stack is discussed. In this concept, a second laminate, called Thermal Power Plane (TPP), is attached through solder rails to the top chip of the stack. The TPP provides efficient heat removal and current feed in the out-of-plane and the in-plane direction, respectively. Accordingly, the number of electrical interconnects to the chip stack can be doubled, enabling higher off-stack communication. An interconnect count analysis was performed for a two-die stack with cores in the top and cache in the bottom chip. The power to the top and the bottom chip is provided from the TPP and the bottom laminate, respectively. In this case, all power through-silicon vias (TSVs) can be eliminated, which would otherwise cover 3.3% of the bottom chip area. In addition, the design of the TSVs can be optimized for signaling only. The use of two laminates also enables individual test & burn-in of the dies prior to stack formation, potentially improving the yield by joining only known good dies. The feasibility of the concept is supported by thermal and electrical finite-element analysis. An 8-layer coreless laminate with stacked build-up vias, extending between both sides of the substrate, was considered as implementation of the TPP. The thermal performance of the dual-side EIC topology outperforms that of the classical single-side EIC approach by 5 Kmm2/W, when considering bar-shaped copper planes in the TPP and elongated top interconnects, called rails. A voltage uniformity to the top chip of better than 2% of the supply voltage can be provided for all TPP designs.