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Dive into the research topics where Tsyr-Chyang Ho is active.

Publication


Featured researches published by Tsyr-Chyang Ho.


Archive | 2007

Delay locked loop

Thomas H. Lee; Kevin S. Donnelly; Tsyr-Chyang Ho; Mark G. Johnson


Archive | 2000

Bus system optimization

Jared L. Zerbe; Kevin S. Donnelly; Stefanos Sidiropoulos; Donald C. Stark; Mark Horowitz; Leung Yu; Roxanne Vu; Jun Kim; Bruno W. Garlepp; Tsyr-Chyang Ho; Benedict Lau


Archive | 1994

Voltage controlled phase shifter with unlimited range

Thomas H. Lee; Kevin S. Donnelly; Tsyr-Chyang Ho


Archive | 1995

Amplifier with active duty cycle correction

Thomas H. Lee; Kevin S. Donnelly; Tsyr-Chyang Ho


Archive | 2003

Integrated circuit with timing adjustment mechanism and method

Jared L. Zerbe; Kevin S. Donnelly; Stefanos Sidiropoulos; Donald C. Stark; Mark Horowitz; Leung Yu; Roxanne Vu; Jun Kim; Bruno W. Garlepp; Tsyr-Chyang Ho; Benedict Lau


Archive | 2006

Calibrated data communication system and method

Jared L. Zerbe; Kevin S. Donnelly; Stefanos Sidiropoulos; Donald C. Stark; Mark Horowitz; Leung Yu; Roxanne Vu; Jun Kim; Bruno W. Garlepp; Tsyr-Chyang Ho; Benedict Lau


Archive | 2002

Phase detector with minimized phase detection error

Kevin S. Donnelly; Thomas H. Lee; Tsyr-Chyang Ho


Archive | 2009

Memory system with calibrated data communication

Jared L. Zerbe; Kevin S. Donnelly; Stefanos Sidiropoulos; Donald C. Stark; Mark Horowitz; Leung Yu; Roxanne Vu; Jun Kim; Bruno W. Garlepp; Tsyr-Chyang Ho; Benedict Lau


Archive | 2016

Memory controller that calibrates a transmit timing offset

Jared L. Zerbe; Kevin S. Donnelly; Stefanos Sidiropoulos; Donald C. Stark; Mark Horowitz; Leung Yu; Roxanne Vu; Jun Kim; Bruno W. Garlepp; Tsyr-Chyang Ho; Benedict Lau


Archive | 2015

FLASH MEMORY CONTROLLER WITH CALIBRATED DATA COMMUNICATION

Jared L. Zerbe; Kevin S. Donnelly; Stefanos Sidiropoulos; Donald C. Stark; Mark Horowitz; Leung Yu; Roxanne Vu; Jun Kim; Bruno W. Garlepp; Tsyr-Chyang Ho; Benedict Lau

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