Stephan Senz

Epitaxial growth of silicon nanowires using an aluminium catalyst

Silicon nanowires have been identified as important components for future electronic and sensor nanodevices1. So far gold has dominated as the catalyst for growing Si nanowires via the vapour–liquid–solid (VLS) mechanism2,3,4,5. Unfortunately, gold traps electrons and holes in Si and poses a serious contamination problem for Si complementary metal oxide semiconductor (CMOS) processing. Although there are some reports on the use of non-gold catalysts6,7,8,9 for Si nanowire growth, either the growth requires high temperatures and/or the catalysts are not compatible with CMOS requirements. From a technological standpoint, a much more attractive catalyst material would be aluminium, as it is a standard metal in Si process lines. Here we report for the first time the epitaxial growth of Al-catalysed Si nanowires and suggest that growth proceeds via a vapour–solid–solid (VSS) rather than a VLS mechanism. It is also found that the tapering of the nanowires can be strongly reduced by lowering the growth temperature.

Extended Arrays of Vertically Aligned Sub-10 nm Diameter [100] Si Nanowires by Metal-Assisted Chemical Etching

Large-area high density silicon nanowire (SiNW) arrays were fabricated by metal-assisted chemical etching of silicon, utilizing anodic aluminum oxide (AAO) as a patterning mask of a thin metallic film on a Si (100) substrate. Both the diameter of the pores in the AAO mask and the thickness of the metal film affected the diameter of SiNWs. The diameter of the SiNWs decreased with an increase of thickness of the metal film. Large-area SiNWs with average diameters of 20 nm down to 8 nm and wire densities as high as 10 (10) wires/cm (2) were accomplished. These SiNWs were single crystalline and vertically aligned to the (100) substrate. It was revealed by transmission electron microscopy that the SiNWs were of high crystalline quality and showed a smooth surface.

Individually addressable epitaxial ferroelectric nanocapacitor arrays with near Tb inch −2 density

Ferroelectric materials have emerged in recent years as an alternative to magnetic and dielectric materials for nonvolatile data-storage applications. Lithography is widely used to reduce the size of data-storage elements in ultrahigh-density memory devices. However, ferroelectric materials tend to be oxides with complex structures that are easily damaged by existing lithographic techniques, so an alternative approach is needed to fabricate ultrahigh-density ferroelectric memories. Here we report a high-temperature deposition process that can fabricate arrays of individually addressable metal/ferroelectric/metal nanocapacitors with a density of 176 Gb inch(-2). The use of an ultrathin anodic alumina membrane as a lift-off mask makes it possible to deposit the memory elements at temperatures as high as 650 degrees C, which results in excellent ferroelectric properties.

Ordered arrays of vertically aligned [110] silicon nanowires by suppressing the crystallographically preferred etching directions.

The metal-assisted etching direction of Si(110) substrates was found to be dependent upon the morphology of the deposited metal catalyst. The etching direction of a Si(110) substrate was found to be one of the two crystallographically preferred 100 directions in the case of isolated metal particles or a small area metal mesh with nanoholes. In contrast, the etching proceeded in the vertical [110] direction, when the lateral size of the catalytic metal mesh was sufficiently large. Therefore, the direction of etching and the resulting nanostructures obtained by metal-assisted etching can be easily controlled by an appropriate choice of the morphology of the deposited metal catalyst. On the basis of this finding, a generic method was developed for the fabrication of wafer-scale vertically aligned arrays of epitaxial [110] Si nanowires on a Si(110) substrate. The method utilized a thin metal film with an extended array of pores as an etching catalyst based on an ultrathin porous anodic alumina mask, while a prepatterning of the substrate prior to the metal depostion is not necessary. The diameter of Si nanowires can be easily controlled by a combination of the pore diameter of the porous alumina film and varying the thickness of the deposited metal film.

Colossal injection of catalyst atoms into silicon nanowires

The incorporation of impurities during the growth of nanowires from the vapour phase alters their basic properties substantially, and this process is critical in an extended range of emerging nanometre-scale technologies. In particular, achieving precise control of the behaviour of group III and group V dopants has been a crucial step in the development of silicon (Si) nanowire-based devices. Recently it has been demonstrated that the use of aluminium (Al) as a growth catalyst, instead of the usual gold, also yields an effective p-type doping, thereby enabling a novel and efficient route to functionalizing Si nanowires. Besides the technological implications, this self-doping implies the detachment of Al from the catalyst and its injection into the growing nanowire, involving atomic-scale processes that are crucial for the fundamental understanding of the catalytic assembly of nanowires. Here we present an atomic-level, quantitative study of this phenomenon of catalyst dissolution by three-dimensional atom-by-atom mapping of individual Al-catalysed Si nanowires using highly focused ultraviolet-laser-assisted atom-probe tomography. Although the observed incorporation of the catalyst atoms into nanowires exceeds by orders of magnitude the equilibrium solid solubility and solid-solution concentrations in known non-equilibrium processes, the Al impurities are found to be homogeneously distributed in the nanowire and do not form precipitates or clusters. As well as the anticipated effect on the electrical properties, this kinetics-driven colossal injection also has direct implications for nanowire morphology. We discuss the observed strong deviation from equilibrium using a model of solute trapping at step edges, and identify the key growth parameters behind this phenomenon on the basis of a kinetic model of step-flow growth of nanowires. The control of this phenomenon provides opportunities to create a new class of nanoscale devices by precisely tailoring the shape and composition of metal-catalysed nanowires.

Structural and electrical anisotropy of (001)-, (116)-, and (103)-oriented epitaxial SrBi2Ta2O9 thin films on SrTiO3 substrates grown by pulsed laser deposition

Epitaxial SrBi2Ta2O9 (SBT) thin films with well-defined (001), (116), and (103) orientations have been grown by pulsed laser deposition on (001)-, (011)-, and (111)-oriented Nb-doped SrTiO3 substrates. X-ray diffraction pole figure and φ-scan measurements revealed that the three-dimensional epitaxial orientation relation SBT(001)‖SrTiO3(001), and SBT[110]‖SrTiO3[100] is valid for all cases of SBT thin films on SrTiO3 substrates, irrespective of their orientations. Atomic force microscopy images of the c-axis-oriented SBT revealed polyhedron-shaped grains showing spiral growth around screw dislocations. The terrace steps of the c-axis-oriented SBT films were integral multiples of a quarter of the lattice parameter c of SBT (∼0.6 nm). The grains of (103)-oriented SBT films were arranged in a triple-domain configuration consistent with the symmetry of the SrTiO3(111) substrate. The measured remanent polarization (2Pr) and coercive field (2Ec) of (116)-oriented SBT films were 9.6 μC/cm2 and 168 kV/cm, respec...

Ferroelectric nanotubes fabricated using nanowires as positive templates

The authors report on fabrication and electrical characterization of ferroelectric nanotubes and metal-ferroelectric-metal composite nanotubes using silicon and ZnO nanowires as positive templates. Nanotubes of high aspect ratio with a minimum inner diameter of about 100nm and a length ranging from 0.5μm to a few microns have been obtained by magnetron sputtering and/or pulsed laser deposition. Metal-ferroelectric one-dimensional structures were characterized by piezoelectric scanning probe microscopy, showing piezoelectric hysteresis loops and ferroelectric switching. The presented fabrication approach can be used to fabricate three-dimensional capacitors for ferroelectric nonvolatile memories as well as nanosize piezoelectric scanners and actuators.

Room-temperature observation of high-spin polarization of epitaxial CrO2(100) island films at the Fermi energy

Epitaxial CrO2(100) island films have been grown on TiO2(100) substrates by a chemical-vapor deposition technique. Well-controlled surface and interface properties of the CrO2(100) films were confirmed by scanning tunneling microscopy and transmission electron microscopy, respectively. Spin- and angle-resolved photoemission spectroscopy at room temperature revealed an energy gap of about 2 eV below Fermi level EF for spin-down electrons and a spin polarization of about +95% at EF. After extended sputtering, the spin polarization can be recovered from about +10% up to +85% upon annealing.

BaBi4Ti4O15 ferroelectric thin films grown by pulsed laser deposition

BaBi4Ti4O15 (BBiT) is an n=4 member of the Bi-layer-structured ferroelectric oxide family (Aurivillius phases). BBiT thin films with preferred orientations have been grown on epitaxial conducting LaNiO3 electrodes on (001) SrTiO3 by pulsed laser deposition. Cross-section electron microscopy analysis reveals that the films consist of ct-axis oriented regions and mixed at- and ct-axis oriented regions. The mixed at- and ct-axis oriented regions show high surface roughness due to the rectangular crystallites protruding out of the surface, whereas the ct-axis oriented regions show a smooth surface morphology. In the mixed at- and ct-axis oriented regions, the BBiT films exhibit saturated ferroelectric hysteresis loops with remnant polarization Pr of 2 μC/cm2 and coercive field Ec of 60 kV/cm and no polarization fatigue up to 108 cycles. The regions having ct-axis orientation with a smooth surface morphology exhibit a linear P–E curve. The results show that the ferroelectric properties of a planar capacitor co...

Atomically Smooth p-Doped Silicon Nanowires Catalyzed by Aluminum at Low Temperature

Silicon nanowires (SiNWs) are powerful nanotechnological building blocks. To date, a variety of metals have been used to synthesize high-density epitaxial SiNWs through metal-catalyzed vapor phase epitaxy. Understanding the impact of the catalyst on the intrinsic properties of SiNWs is critical for precise manipulation of the emerging SiNW-based devices. Here we demonstrate that SiNWs synthesized at low-temperature by ultrahigh vacuum chemical vapor deposition using Al as a catalyst present distinct morphological properties. In particular, these nanowires are atomically smooth in contrast to rough {112}-type sidewalls characteristic of the intensively investigated Au-catalyzed SiNWs. We show that the stabilizing effect of Al plays the key role in the observed nanowire surface morphology. In fact, unlike Au which induces (111) and (113) facets on the nanowire sidewall surface, Al revokes the reconstruction along the [112] direction leading to equivalent adjacent step edges and flat surfaces. Our finding sets the lower limit of the Al surface density on the nanowire sidewalls at ∼2 atom/nm(2). Additionally, despite using temperatures of ca. 110-170 K below the eutectic point, we found that the incorporation of Al into the growing nanowires is sufficient to induce an effective p-type doping of SiNWs. These results demonstrate that the catalyst plays a crucial role is shaping the structural and electrical properties of SiNWs.