Mohsen Alavi

A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.

A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell

A leading edge 90 nm technology with 1.2 nm physical gate oxide, 50 nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k carbon-doped oxide (CDO) for high performance dense logic is presented. Strained silicon is used to increase saturated NMOS and PMOS drive currents by 10-20% and mobility by >50%. Aggressive design rules and unlanded contacts offer a 1.0 /spl mu/m/sup 2/ 6-T SRAM cell using 193 nm lithography.

A PROM element based on salicide agglomeration of poly fuses in a CMOS logic process

A novel programmable element has been developed and evaluated for state of the art CMOS processes. This element is based on agglomeration of the Ti-silicide layer on top of poly fuses. Various aspects of this programmable device including characterization and optimization of physical and electrical aspects of the element, programming yield, and reliability have been studied. Development of a novel programming and sensing circuit is also included.

A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects

A leading edge 130 nm generation logic technology with 6 layers of dual damascene Cu interconnects is reported. Dual Vt transistors are employed with 1.5 nm thick gate oxide and operating at 1.3 V. High Vt transistors have drive currents of 1.03 mA//spl mu/m and 0.5 mA//spl mu/m for NMOS and PMOS respectively, while low Vt transistors have currents of 1.17 mA//spl mu/m and 0.6 mA//spl mu/m respectively. Technology design rules allow a 6-T SRAM cell with an area of 2.45 /spl mu/m/sup 2/, while array specific design rule give the densest SRAM reported to date, the 6-T cell has an area of only 2.09 /spl mu/m/sup 2/. Excellent yield and performance is demonstrated on a 18 Mbit CMOS SRAM.

An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V

A leading edge 130 nm technology with 6 layers of Cu interconnects and 1.3 V operation has previously been presented (Tyagi et al., 2000). In this work, we enhance the previous technology with the following: transistor improvements which support a 60 nm gate dimension and increased drive current, improved 6-T SRAM device matching to allow low power and high performance operation from 0.7 to 1.4 V, and a 5% linear shrink to reduce the 6-T SRAM cell to 2.00 /spl mu/m/sup 2/ while still using 248 nm lithography. Saturation drive currents of 1.30 mA//spl mu/m for N-channel and 0.66 mA//spl mu/m for P-channel low VT devices are the highest reported to date. Excellent device short channel effects are obtained for the 60 nm gate length devices as measured by the 270 mV threshold voltage and <100 mV/V DIBL. These results have been achieved on both 200 and 300 mm wafers.

Source/drain extension scaling for 0.1 /spl mu/m and below channel length MOSFETs

In this paper, we investigate the scaling of source/drain extension (SDE) depth and SDE to gate overlap for 0.1 /spl mu/m and below MOSFETs. We show for the first time that a minimum SDE to gate overlap of 15-20 nm is needed to prevent drive current (I/sub DSAT/) degradation. We also show for the first time that scaling SDE vertical depths below 30-40 nm results in little to no performance benefit for 0.1 /spl mu/m devices and beyond since any improvement in short channel effects due to reduced charge sharing is offset by a large increase in external resistance and poor gate coupling between the channel and extensions.

Temperature dependence of substrate current and hot carrier-induced degradation at low drain bias

Temperature dependence of substrate current (Isub) and hot carrier lifetime in sub 0.25 /spl mu/m NMOS devices has been evaluated at elevated temperatures. Unlike conventional behaviour, for scaled devices Isub is found to increase with temperature at low drain bias. The transition point to the new behaviour is found to be bias and temperature dependent. The correlation between hot carrier lifetime and Isub has been found to still hold in the new regime. At Vd=1.5 V, this results in 4/spl times/ lower lifetime at 125 C versus 25 C. The lucky electron model is found not to explain the new observations. These findings are consistent with previously reported results on Isub at reduced temperatures and the modeling of statistical distribution of carrier energy at low drain bias.

Effect Of MOS Device Scaling On Process Induced Gate Charging

Plasma induced gate charging damage is evaluated for advanced processes with ultra thin oxides. It is found that thinning the gate oxide results in increased damage up to a point. Beyond thiat, damage is reduced significantly due to direct tunneling current. Additionally, it is shown that diodes with breakdown voltages higher than oxide breakdown still offer protection against damage (piroportional to their area) while gated diodes offer improved protection. Elevated temperature during charging has been found to increase oxide degradation and PMOS structures have been found much more susceptible. Physical models are provided for these findings.

Minority-carrier injection in Pt&#8212;Si Schottky-barrier diodes at high current densities

This paper presents a study of minority-carrier injection in platinum-silicide Schottky-barrier diodes at room temperature under steady-state dc bias for current densities extending to 105A /cm2. The phenomenon is experimentally investigated by measuring the minority-carrier storage using a reverse-recovery technique and by measuring the conductivity-modulated J-V characteristics. The theoretical treatment is based on a one-dimensional numerical simulation of the equations governing steady-state dc carrier transport in the device, corrected for lateral voltage drop in the n+buried layer. Simulation results are in good agreement with the measured carrier storage as well as the J-V characteristics. The minority-carrier injection ratio is calculated to be about 0.3 percent at 105A/cm2. This degree of injection causes appreciable conductivity modulation and leads to stored charge densities on the order of 10-5C/cm2. For reverse switching currents on the order of 104A/cm2, the majority of excess carriers were observed to discharge during the first 2 ns of reverse-recovery while a secondary discharge of minority carriers, lasting a few additional nanoseconds, was observed.

AC/DC characterization of NMOS and PMOS hot-carrier-induced degradation under AC/DC stress

The AC/DC measurements of NMOS and PMOS I/sub dsat/ shifts are compared following DC stress. The results of the I/sub dsat/ shifts are found to be the same. The AC I/sub dsat/ measurements were performed under a variety of different conditions (varying frequency, amplitude, and base level) and showed that hot-carrier-induced interfaced states are shallow and fast ( >