Stephen L. Wong

Impact of Scaling on MOS Analog Performance

A first-order analysis of the impact of scaling on MOS analog performance under moderate scaling conditions is presented in this paper. Assuming a polysilicon gate ion-implanted MOS technology, quasi-constant voltage (QCV) scaling is shown to be the optimal scaling law, offering the best overall analog performance and resulting in an increase in functional density, gain-bandwidth product with a moderate degradation in gain, and signal-to-noise ratio. The first-order analysis agrees fairly well with computer simulation. A typical case study shows that under moderate scaling conditions, CMOS can generally offer a higher voltage gain when compared to depletion load NMOS and is the preferred technology for scaled analog implementations.

Design of a 60-V 10-A intelligent power switch using standard cells

A small, low-cost, intelligent power switch (IPS) for use in automotive applications is described. The chip integrates a 60-V 30-m Omega power device with a comprehensive set of protection functions using a mixed-voltage standard cell methodology and only 11 mask layers. >

A 2.7-5.5 V, 0.2-1 W BiCMOS RF driver amplifier IC with closed-loop power control and biasing functions

A 800-900 MHz BiCMOS driver amplifier with 30 dB gain is integrated with various functions of a power control loop which includes a peak power detector, an integrator filter, gain control circuitry, and a voltage regulator for biasing a discrete power device. To add to its versatility, the IC is pad-programmable to deliver either 0.25 W/0.5 W/1.0 of RF power while maintaining a power added efficiency of 35 to 40% in each case. This has been shown to be useful in creating 1-4 W power amplifier solutions with over 50% efficiency. In closed-loop configuration, this IC provides better than 1 dB of output power control over a dynamic range of 25 dB.