Satyendranath Mukherjee

Dependence of breakdown voltage on drift length and buried oxide thickness in SOI RESURF LDMOS transistors

The dependence of avalanche breakdown voltage on the drift region length and buried oxide thickness of thin silicon-on-insulator (SOI) LDMOS transistors is reported. An ideal relationship between breakdown voltage and drift length is derived. Experimental SOI LDMOS transistors with near ideal breakdown voltages in the short-drift-length regime have been realized. Specifically, 380 V was achieved in a drift length of 20 mu m. Thin buried oxides are shown to be a major cause of deviation from this ideal. Experimental results verify this finding. An 860-V LDMOS transistor made in a 0.2 mu m-thick SOI layer is reported.<<ETX>>

High performance 600 V smart power technology based on thin layer silicon-on-insulator

A high-performance 600 V smart power technology has been developed in which novel lateral double-diffused MOS transistors (LDMOS) are merged with a BiCMOS process flow for the construction of power integrated circuits on bonded silicon-on-insulator (BSOI) substrates. All active and passive device structures have been optimized for fabrication on BSOI layers which are less than 1.5 /spl mu/m-thick, with buried oxide layers in the range of 2.0 to 3.0 /spl mu/m-thick. Complete dielectric isolation processing is straightforward due to the use of a thin SOI active device layer. A dual field plate design of the high-voltage devices results in at least a factor-of-two reduction in specific on-resistance over conventional LDMOS structures for a given breakdown voltage.

Comparison of junction-isolated and soi high-voltage devices operating in the source-follower mode

Recent developments in high-voltage devices have made it feasible to realize monolithic power integrated circuits that combine high voltage devices with control, level shifter and logic function on a single chip. One of the important uses of such circuits is to assemble bridge circuits, which are needed whenever waveforms of arbitrary shape and frequency have to be synthesized. Typical examples are electronic ballasts and motor drives. In such circuits the source of the upper of the two switches, the high-side transistor, has to float above ground potential. In this work we have studied, both theoretically and experimentally, the behavior of junction-isolated (JI) and silicon-on-insulator (SOI) devices in applications involving the source-follower configuration at voltages up to 700 V. We find that the SO1 devices exhibit significantly lower on-resistance under source-high conditions than do JI devices, and that this effect is especially pronounced at high source bias voltages. The devices used in this study were LDMOS transistors, with off-state breakdown voltages of 500-700V (Fig. 1). Both types of devices were designed according to the RESURF principle in order to maximize the breakdown voltage [l, 21. Measurements of the on-state Id - Vh characteristic of the JI transistor in common-source and source-high configurations indicate that, in the latter case, the difference between the substrate and source potentials causes the drift region of the LDMOS transistor to become depleted, resulting in an increase of the on-resistance. In the case of the the SO1 device, however, an inversion layer forms at the buried oxide-SO1 layer interface. Once strong inversion is established, the width of the depletion region does not increase with further increase in the substrate potential, so that the remainder of the SO1 layer remains undepleted. Consequently, relatively little change occurs in the on-resistance of the SO1 device after the initial onset of the inversion layer. As a consequence of the RESURF principle which imposes conditions on the drift region charge, the specific on-resistances of the JI and SO1 devices in common-source configuration are comparable. However, as the source potential increases, the SO1 on-resistance increases slightly and saturates to a constant value, while the on-resistance of the JI device increases much more drastically (Fig. 2). This effect in JI devices can be alleviated to some extent by design modifications, such as the use of a lightly-doped substrate, a thicker epitaxial layer or inclusion of additional charge-compensating regions [3]. However, the effectiveness of such modifications at very high voltages is limited. For this reason, the source-follower operation becomes more difficult to realize in very-high- breakdown-voltage JI devices. This behavior has important implications on the ability to integrate high-voltage source-follower devices in power integrated circuits. The substantial increase in the on-resistance of the JI transistor would necessitate a correspondingly large increase in the device area, making the integration impractical. Such a limitation does not exist in the SO1 technology, which is thus more suitable for integrating multiple power devices on a single chip.

600 V power conversion system-on-a-chip based on thin layer silicon-on-insulator

An integrated 600 V power conversion system is described based on smart power technology which combines novel lateral high-voltage RESURF transistor structures and a merged bipolar/CMOS/DMOS process flow on thin-layer SOI substrates. A new high-voltage SOI LDMOS device structure is presented which results in a factor-of-two decrease in specific on-resistance and a factor-of-two improvement in source-follower saturated current, thus overcoming a key limitation of integrated thin-layer technology. This opens new application areas for thin-layer SOI, such as lighting electronics, power modules, motor control, and others, a significant development for the integration of power conversion systems.

Thin-layer silicon-on-insulator high-voltage PMOS device and application

We present a thin-layer silicon-on-insulator (SOI) high-voltage PMOS device structure and measured performance characteristics. The all-implanted device structure supports voltage by multi-dimensional depletion from a combination of implanted surface pn junctions and MOS capacitor structures formed with multi-level dielectric deposition and metallization. A graded-doped body region has been optimized for application voltages from 100-600 V, and the structure has been evaluated in applications including high-voltage level shifting, low-dissipation bias networks, and high-voltage high-frequency class AB power output stages. The integrated high-voltage PMOS device structure enables low-power, high voltage, and high-speed complementary circuit topologies to be realized in a thin-layer SOI process flow, improving circuit efficiency and expanding the application base for thin-layer technology.

A scaled CMOS-compatible smart power IC technology

An integrated VDMOS-based PIC process was developed to increase the cost effectiveness and performance of 60 V high current circuits. Compact 60 V CMOS elements and a 140 m Omega -mm/sup 2/ VDMOS were integrated into a 3 mu m CMOS process using only one additional mask. This increased level of integration allowed the use of a cell-based ASPIC (application-specific power IC) methodology as an attractive alternative to conventional full-custom approaches. This was demonstrated in the development of a 10 A intelligent power switch for automotive applications.<<ETX>>

A high current power IC technology using trench DMOS power device

A high-current power IC (PIC) technology that combines trench DMOS power devices with CMOS control is described. In the CMOS section, both high-voltage (60 V) and low-voltage (10 V) P- and N-channel MOS transistors allow dense control as well as high-voltage operation. The trench DMOS power device has a breakdown voltage of over 60 V and specific on resistance of 80 m Omega -mm/sup 2/. Using this technology, a high side switch PIC has been demonstrated for automotive applications. The low specific R/sub on/ and the dense control capability enable the PIC to handle up to 10 A of current with a die size of 8 mm/sup 2/.<<ETX>>

A thin-layer high-voltage silicon-on-insulator hybrid LDMOS/LIGBT device

We present a new lateral high-voltage silicon-on-insulator (SOI) power device structure which is a hybrid combination of bipolar and unipolar current flow segments. The hybrid LDMOS/LIGBT device shows a substantial performance advantage over LDMOS due to voltage-dependent conductivity-modulation and a resultant increase in maximum source-follower current capability. When fabricated in an integrated SOI process flow, the LDMOS/LIGBT hybrid device reduces the power device area by 25-50% for many applications, resulting in cost-effective integration and miniaturization of power conversion systems that use a half-bridge topology.

600 V single-chip power conversion system based on thin layer silicon-on-insulator

Summary form only given. An integrated 600 V power conversion circuit is described based on smart power technology which combines novel lateral high-voltage RESURF transistor structures and a merged bipolar/CMOS/DMOS process flow on thin-layer SOI substrates. A modular process flow provides for the integration of half-bridge power stages along with level shifting and lowand medium-voltage control. This opens new application areas for thin-layer SOI, such as lighting electronics, power modules, motor control, etc., and is a significant development for the integration of power conversion systems.

Measurement of minority carrier diffusion length and lifetime in SOI devices by flying spot laser scanner as a function of residual misfit

The recombination properties of minority carriers determine the basic electronic properties of SOI materials and control the performance of a variety of SOI devices. Knowledge of the minority carrier recombination characteristics and its correlation to residual defect density is important for the evaluation of SOI technologies with varying degrees of crystal lattice imperfection. In this work we first describe a technique based on a flying spot laser scan microscope for the measurement of minority carrier diffusion length, L, and lifetime, /spl tau/, in SOI high voltage diodes. In our experiment, laser light of 633 nm wavelength is absorbed in the Si material through the generation of electron-hole pairs which, if generated in the depletion region, are separated by the high local field to give rise to a photocurrent that can be measured.<<ETX>>