Stephen Mick

Demystifying 3D ICs: the pros and cons of going vertical

This article provides a practical introduction to the design trade-offs of the currently available 3D IC technology options. It begins with an overview of techniques, such as wire bonding, microbumps, through vias, and contactless interconnection, comparing them in terms of vertical density and practical limits to their use. We then present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rents rule. Next, we provide a more detailed design example of inductively coupled interconnects, with measured results of a system fabricated in a 0.35-/spl mu/m technology and an analysis of misalignment and crosstalk tolerances. Lastly, we present a case study of a fast Fourier transform (FFT) placed and routed in a 0.18-/spl mu/m through-via silicon-on-insulator (SOI) technology, comparing the 3D design to a traditional 2D approach in terms of wire length and critical-path delay.

4 Gbps high-density AC coupled interconnection

AC coupled interconnects enable multi-gigabit-persecond communication data rates between integrated circuits with very high pin counts and low power consumption. AC coupling can be realized with either series capacitive or inductive coupling elements. Capacitive AC coupling offers better performance when low power I/O buffers are required and when there is sufficient area to dedicate to coupling capacitors in the top-level metal of each IC. At a slight expense of circuit complexity, inductive AC coupling can be used to bring I/O pad pitches down to 75 /spl mu/m and maintain a controlled impedance connection. A novel physical structure, buried solder bumps, are used as a solution for providing DC power and ground connections across the same surface as the AC connections. When used in conjunction with NRZ-tolerant receivers, and current-mode signaling, highly effective interconnect structures can be built. As well as presenting both physical and circuit aspects of this work, experimental results are shown.

3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver

A 120-mV/sub ppd/ low swing pulse receiver is presented for AC coupled interconnect (ACCI). Using this receiver, 3Gb/s chip-to-chip communication is demonstrated through a wire-bonded ACCI channel with 150-fF coupling capacitors, across 15-cm FR4 microstrip lines. A test chip was fabricated in TSMC 0.18-/spl mu/m CMOS technology and the driver and pulse receiver dissipate 15-mW power per I/O at 3 Gb/s, with a bit error rate less than 10/sup -12/. First-time demonstration of a flip-chip ACCI is also presented, with both the AC and DC connections successfully integrated between the flipped chip and the multichip module (MCM) substrate by using the buried bump technology. For the flip-chip ACCI, 2.5 Gb/s/channel communication is demonstrated across 5.6 cm of transmission line on a MCM substrate.

2.8 Gb/s inductively coupled interconnect for 3D ICs

An inductively coupled interconnect scheme for vertical signaling in 3D ICs is demonstrated. Test chips were fabricated in TSMC 0.35 /spl mu/m CMOS technology, then thinned and stacked. For 90 /spl mu/m thick chips using 150 /spl mu/m inductors, the transceiver communicates NRZ signals at 2.8Gb/s, and tolerates up to 50 /spl mu/m misalignment. TX and RX power dissipation are 10.0 mW and 37.6 mW, respectively. The transceiver circuit does not require a clock to recover the data and is able to maintain less than 100 ps jitter at the RX output.

Buried bump and AC coupled interconnection technology

A novel physical structure, buried solder bumps, is introduced that solves the compliance problems that exist in scaling present area array technologies to ever-higher densities. In this technique, buried bumps provide dc connections between integrated circuits and substrates and ac coupled interconnections provide paths for ac signals across the same interface. This approach requires co-design of packaging and circuits and meets the growing demands for both interconnect density and bandwidth. AC coupled interconnection arrays can be built with pitches for ac signals below 100 /spl mu/m and data rates of 6 Gb/s per I/O. This paper presents the physical and circuit aspects of this work as well as measured results from capacitively-coupled circuits fabricated in Taiwan semiconductor manufacturing Company (TSMC) 0.35-/spl mu/m technology. Simulated results from capacitively-coupled circuits in TSMC 0.18 /spl mu/m are also presented.

Fully integrated AC coupled interconnect using buried bumps

Demonstrated is the fully integrated chip and package technology proposed in ACCI. ACCI provides power and ground distribution by using a buried solder bump, and data transmission through capacitors formed between the chip and package.

A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver

A new differential pulse receiver is demonstrated for AC coupled interconnect (ACCI), which enables the highest data rate, at 6Gb/s/channel (36Gb/s aggregate), for capacitively coupled systems using pulse signaling. The system works across FR4 printed circuit board (PCB) interconnect lengths of up to 30cm with coupling capacitors from 95fF to 165fF, while dissipating only 1.97mW/Gbps for the entire differential transceiver (0.83pJ/bit for the transmitter and 1.23pJ/bit for the receiver)

AC coupled interconnect using buried bumps for laminated organic packages

Various techniques for providing non-contacting, interchip signaling have been demonstrated, such as: ACCI presented in S. Mick et al. (2002) and L. Luo et al. (2005), proximity communication based in R. Drost et al. (2004), and wireless superconnect (WSC) reported in K. Kanda et al. (2004). ACCI using buried bumps is the only technology that provides a manufacturable solution for non-contacting I/O signaling by integrating high-density, low inductance power and ground distribution with high-density, high-speed I/O. This completely integrated solution has been demonstrated at 2.5Gb/s/channel across 5.6cm of micro-strip transmission line using 0.35mum CMOS ICs that were flip-chip attached onto a silicon MCM-D as presented in J. Wilson et al. (2005)

A High K Nanocomposite for High Density Chip-to-Package Interconnections

AC-coupled interconnects (ACCI) is a very exciting technology for achieving high-density chip-to-package interconnects while simultaneously providing a simple, mechanically robust interface. The technology combines the stress-relieving ‘underfill’ layer with the dielectric medium for capacitive coupling. For good AC coupling, it is desirable for the underfill material to have a permittivity around 20 at operating frequencies. However, there is a lack of microwave frequency data for high permittivity ceramic-polymer composite systems in the literature. This paper describes the development and microwave frequency characterization of high K nanocomposite underfill. For composite thick film preparation, 200 nm BaTiO 3 nano-sized powder and photosensitive epoxy were used. The thermal behavior of composites was evaluated by DSC (differential scanning calorimetry). Dielectric properties were evaluated as a function of ceramic loading and curing temperature. The microwave dielectric properties were measured from 45 MHz up to 26.5 GHz to extract the capacitance and quality factor of the capacitor over the frequencies of interest using floating plate capacitors and T-resonator CPW structures. The permittivity was found to be ∼ 18 up to 14 GHz and the total Q factor of the capacitors was found to be 2 at 26.5 GHz for BaTiO 3 (30 vol%)-epoxy composite. Dielectric loss was found to be 0.3 at 3 GHz, which would satisfactorily allow signaling well into the muti-gigabits range. The high K nanocomposite shows higher permittivity compared to materials currently used (air, K=1 or SiO 2 , K∼3.9) in capacitively coupled interconnects for chip-to-package communications.

Inductively Coupled Connectors and Sockets for Multi-Gb/s Pulse Signaling

Multi-Gb/s pulse signaling is demonstrated with inductively coupled interconnects across packaging interfaces. This has application in realizing submillimeter pitch, true zero insertion force (ZIF) surface mount connectors, and sockets. The signaling data rate achieved in this system is from 1 to 8.5 Gbps, which depends on the 3-dB coupling frequency of the composite channel consisting of the inductive interconnections and the transmission lines. This paper presents the results of a set of experiments demonstrating this capability and describes the principles behind the design of inductively coupled sockets and connectors.