Jiuun-Jer Yang

A new approach for characterizing structure-dependent hot-carrier effects in drain-engineered MOSFET's

In this paper, we have demonstrated successfully a new approach for evaluating the hot-carrier reliability in submicron LDD MOSFET with various drain engineering. It was developed based on an efficient charge pumping measurement technique along with a new criterion. This new criterion is based on an understanding of the interface state (N/sub it/) distribution, instead of substrate current or impact ionization rate, for evaluating the hot-carrier reliability of drain-engineered devices. The position of the peak N/sub it/ distribution as well as the electric field distribution is critical to the device hot-carrier reliability. From the characterized N/sub it/ spatial distribution, we found that the shape of the interface state distribution is similar to that of the electric field. Also, to suppress the spacer-induced degradation, we should keep the peak values of interface state away from the spacer region. In our studied example, for conventional LDD device, sidewall spacer is the dominant damaged region since the interface state in this region causes an additional series resistance which leads to drain current degradation. LATID device can effectively reduce hot-carrier effect since most of the interface states are generated away from the gate edge toward the channel region such that the spacer-induced resistance effect is weaker than that of LDD devices.

A new approach to modeling the substrate current of pre-stressed and post-stressed MOSFET's

In this paper, we propose a closed form expression of a new and accurate analytical substrate current model for both pre-stressed and post-stressed MOSFETs. It was derived based on the concept of effective electric field, which gives a more reasonable impact ionization rate in the lucky-electron model. This effective electric field, composed by two experimentally determined parameters, can be regarded as a result of nonlocal heating effects within devices. This model shows a significant improvement to the conventional local field model. One salient feature of the present model is that it allows us to characterize the time evolution of the substrate current of stressed MOSFETs for the first time. Experimental verification for a wide variety of MOSFETs with effective channel lengths down to 0.3 /spl mu/m shows that the new model is very accurate and is feasible for any kind of MOS device with different drain structures. The present model can be applied to explore the hot carrier effect in designing submicrometer MOS devices with emphasis on the design optimization of a device drain engineering issue. In addition, the present model is well suited for device reliability analysis and circuit level simulations. >

Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack

For the first time, a shallow trench isolation (STI)-induced enhanced degradation in pMOSFETs for ultrathin gate oxide devices has been observed. The I/sub D/ degradation is enhanced as a reduction in the gate width and the hot carrier (HC) or negative bias temperature instability (NBTI) effect. Extensive studies have been compared for atomic layer deposition (ALD)-grown and plasma-treated oxide pMOSFETs. Different temperature dependences were observed. At room temperature, hole trap is dominant for the device degradation, in which hole-trap-induced V/sub T/ is significant, whereas at high temperature under NBTI stress, interface trap becomes more significant, which dominates the device I/sub D/ degradation. In addition, the V/sub T/ rolloff can be modeled as a width narrowing effect specifically for STI. More importantly, the NBTI-induced interface/oxide traps are strongly related to the hydrogen and N/sub 2/ content in the gate oxide formation process. The interface trap generation is suppressed efficiently using the ALD-grown gate oxide. These results provide a valuable guideline for the understanding of the HC and NBTI reliabilities in an advanced ALD-grown gate oxide processes/devices.

New Degradation Mechanisms of Width-Dependent Hot Carrier Effect in Quarter-Micron Shallow-Trench-Isolated p-Channel Metal-Oxide-Semiconductor Field-Effect-Transistors

In this study, width-dependent hot-carrier degradation in the p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) with shallow-trench-isolation (STI) is presented. Results show an enhanced drain current degradation with reducing the gate width. A new model and mechanism are proposed to explain the width-dependent hot-carrier (HC) degradation for p-MOSFETs. Based on a two-dimensional channel shortening concept, a new model is developed. The mechanical stress enhanced oxide damage at the STI edge, which will induce channel shortening, is the dominant mechanism for the drain current degradation of the devices after hot-carrier stress. This is a crucial issue for present and future complementary metal-oxide semiconductor (CMOS) ultra-large-scale integration (ULSI), and in particular for high-density dynamic random-access memory (DRAM), fabricated using STI technologies.

A Unified 3-D Mobility Model for the Simulation of Submicron MOS Devices

A calibrated and physically based mobility model is developed for three-dimensional simulation of submicron metal-oxide-semiconductor (MOS) devices, in which the inversion layer mobility is emphasized. This inversion layer mobility can be generalized into a local form, i.e., expressed as functions of the local electric field at each grid point, so that it is well suited for device simulation. The resulting 3-D mobility model accurately characterizes the significant physical scattering effects including the Coulomb screening effect, quantum channel broadening effect, surface roughness scattering, structure-induced lateral surface scattering and velocity saturation limited effects. Results show that this new model can be incorporated into device simulators for accurately predicting drain currents of submicron LDD MOS devices. Moreover, the results compare more favorably with the experimental data than do those for other reported models.

Suppression of the hot carrier effect in designing LATID MOS devices based on a new substrate current model

The gate-and-drain fully-overlap LATID (Large-Tilt-Angle Implanted Drain) structure has been proposed recently and been used in submicron MOS device design to suppress the spacer-induced degradation and improve the device current drivability. So far, none has been provided to study quantitatively the hot carrier effect for various device process conditions such as the implantation of n/sup -/ dosage and angle. A closed form expression of a new and accurate substrate current model is proposed based on the effective electric field concept by considering the overall (2D) electric field distribution within devices, which can be used to explain quantitatively and for predicting the substrate currents of LATID MOS devices. Its utilization in designing a hot carrier resistant device is demonstrated.<<ETX>>

A Consistent Drain And Substrate Current Model Of LDD MOS Devices For Circuit Simulation

This paper describes a Spice-compatible circuit simulation model of submicron LDD MOS devices. It includes an enhanced model of our previous drain current characteristics (UNIMOS) and a new analytical substrate current model. For the drain current characteristics, new features of our previous model has been added for achieving good accuracy and convergency. In addition, the two-dimensional electric field distribution during impact ionization which has much more physical meaning is considered for developing the hot electron model. Thus, a new and accurate substrate current model is proposed based on the so called effactive electric field, instead of the conventional peak electric field concept used by the lucky-electron (LE) theory. Comparison of the modeled results with those of experiment shows excellent match for a wide range of device channel lengths and bias conditions.

Quantitative Investigation of Hot Carrier Induced Drain Current Degradation in Submicron Drain-Engineered Metal-Oxide-Semiconductor Field-Effect-Transistors

Parameters, such as the total amount of hot carrier induced interface states and substrate current, are not sufficient to evaluate hot carrier reliability in drain-engineered metal-oxide-semiconductor field-effect-transistors (MOSFETs). In this paper, for the first time, the distributions of hot carrier induced interface states are physically characterized and incorporated into two-dimensional device simulation to quantitatively study the structure-dependent drain current degradation in submicron MOSFETs, which give us insight into the relationship between degradation modes and device structures. The results show that the hot carrier induced series resistance effect in the sidewall spacer region plays an important role in drain-engineered MOSFETs. A different gate oxide thickness dependence of drain current degradation in thin gate oxide lightly-doped drain (LDD) MOSFETs is observed and is explained as the interface states enhanced series resistance effect in the LDD region.