Chi-Chun Chen

5nm-gate nanowire FinFET

A new nanowire FinFET structure is developed for CMOS device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage cur-rent less than 10 nA/ /spl mu/m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.

25 nm CMOS Omega FETs

Low leakage and low active-power 25 nm gate length C-MOSFETs are demonstrated for the first time with a newly proposed Omega-(/spl Omega/) shaped structure, at a conservative 17-19 /spl Aring/ gate oxide thickness, and with excellent hot carrier immunity. For 1 volt operation, the transistors give drive currents of 1440 /spl mu/A//spl mu/m and 780 /spl mu/A//spl mu/m with off state leakage currents of 8 nA//spl mu/m and 0.4 nA//spl mu/m for N-FET and P-FET, respectively. A low voltage version achieves, at 0.7 V, drive currents of 1300 /spl mu/A//spl mu/m for N-FET and 550 /spl mu/A//spl mu/m for P-FET at an off current of 1 /spl mu/A//spl mu/m. N-FET gate delay (CV/I) of 0.39 ps and P-FET gate delay of 0.88 ps exceed International Technology Roadmap for Semiconductors (ITRS) projections.

Evaluation of plasma charging damage in ultrathin gate oxides

Monitoring of plasma charging damage in ultrathin oxides (e.g., <4 mm) is essential to understand its impact on device reliability. However, it is observed that the shift of several device parameters, including threshold voltage, transconductance, and subthreshold swing, are not sensitive to plasma charging and thus not suitable for this purpose. Consequently, some destructive methods, such as the charge-to-breakdown measurement, are necessary to evaluate plasma damage in the ultrathin oxides.

A 65nm node strained SOI technology with slim spacer

A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current.

Plasma-induced charging damage in ultrathin (3-nm) gate oxides

Plasma-induced damage in various 3-nm-thick gate oxides (i.e., pure oxides and N/sub 2/O-nitrided oxides) was investigated by subjecting both nMOS and pMOS antenna devices to a photoresist ashing step after metal pad definition. Both charge-to-breakdown and gate leakage current measurements indicated that large leakage current occurs at the wafer center as well as the wafer edge for pMOS devices, while only at the wafer center for nMOS devices. These interesting observations could be explained by the strong polarity dependence of ultra thin oxides in charge-to-breakdown measurements of nMOS devices. In addition, pMOS devices were found to be more susceptible to charging damage, which can be attributed to the intrinsic polarity dependence in tunneling current between nand p-MOSFETs. More importantly, our experimental results demonstrated that stress-induced leakage current (SILC) caused by plasma damage can be significantly suppressed in N/sub 2/O-nitrided oxides, compared to pure oxides, especially for pMOS devices. Finally, nitrided oxides were also found to be more robust when subjected to high temperature stressing. Therefore, nitrided oxides appear to be very promising for reducing plasma charging damage in future ULSI technologies employing ultrathin gate oxides.

Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography

For the first time, a novel hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm thick SiON gate dielectric has been developed for advanced SOC applications. 26% (for N-FET) and 35% (for P-FET) improvements of intrinsic gate delay (CV/I) at low gate leakage of 20-40A/cm/sup 2/ have been achieved over previous leading-edge 45nm node version, while maintaining the same sub-threshold leakage (100nA//spl mu/m). 10 times reduction of the leakage can be further modulated by a virtual back-gate control. Fine patterning with line pitch of 90nm by immersion lithography is demonstrated, which features 0.183/spl mu/m/sup 2/ 6T-SRAM cell for 32nm node on-trend scaling.

Reliability of ultrathin gate oxides for ULSI devices

Abstract Ultrathin gate oxide, which is essential for low supply voltage and high driving capability, is indispensable for the continued scaling of ULSI technologies towards smaller and faster devices. Needless to say, the reliability of ultrathin oxide is of major concerns in the manufacturing of the state-of-the-art metal-oxide-semiconductor devices. This paper reviews the reliability issues regarding ultrathin gate oxide for present and future ULSI technologies. Issues including gate leakage current, time-dependent dielectric breakdown, poly-gate depletion, boron penetration, and plasma process-induced damage will be addressed. Several techniques such as nitrided oxide and alternative processes, which are proposed to improve gate oxide reliabilities, are also discussed.

Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack

For the first time, a shallow trench isolation (STI)-induced enhanced degradation in pMOSFETs for ultrathin gate oxide devices has been observed. The I/sub D/ degradation is enhanced as a reduction in the gate width and the hot carrier (HC) or negative bias temperature instability (NBTI) effect. Extensive studies have been compared for atomic layer deposition (ALD)-grown and plasma-treated oxide pMOSFETs. Different temperature dependences were observed. At room temperature, hole trap is dominant for the device degradation, in which hole-trap-induced V/sub T/ is significant, whereas at high temperature under NBTI stress, interface trap becomes more significant, which dominates the device I/sub D/ degradation. In addition, the V/sub T/ rolloff can be modeled as a width narrowing effect specifically for STI. More importantly, the NBTI-induced interface/oxide traps are strongly related to the hydrogen and N/sub 2/ content in the gate oxide formation process. The interface trap generation is suppressed efficiently using the ALD-grown gate oxide. These results provide a valuable guideline for the understanding of the HC and NBTI reliabilities in an advanced ALD-grown gate oxide processes/devices.

Plasma-Process-Induced Damage in Sputtered TiN Metal-Gate Capacitors with Ultrathin Nitrided Oxides

A comprehensive study on plasma-process-induced damage (P2ID) in sputtered TiN metal-gated devices with 4 nm N2O-nitrided oxide was performed. We found that the TiN metal-gated devices exhibit a significant 8 A reduction in the effective oxide thickness, due to physical damage caused by sputtering and/or oxide consumption during the postannealing step. We also found that the postdeposition rapid thermal annealing (RTA) temperature affects both the flat-band voltage (Vfb) and the interface state density (Dit). Furthermore, degradation in the gate-oxide integrity caused by severe charging damage by the additional plasma processes in the TiN metal gate process flow was also observed. The P2ID leads to significant degradation in the charge-to-breakdown and a gate leakage current increase, even for the genuinely robust nitrided oxide used in this study. Finally, N2 plasma posttreatment was proposed as an effective method for suppressing the gate leakage current.

Characterization and optimization of NO-nitrided gate oxide by RTP

The characteristics and reliability of NO-nitrided gate oxide devices were investigated in detail. Light and heavy nitridations were accomplished using rapid thermal annealing (RTA) of SiO/sub 2/ in an NO ambient by varying either annealing temperature or annealing time. The effects of nitridation condition on the charge trapping, interface state generation, low- and high-field mobility, radiation hardness as well as hot-carrier reliability were discussed. We also studied channel hot-carrier effects on the irradiated devices. Results indicate that NO-nitrided devices show a significantly reduced transconductance degradation compared to control devices.