Brian Dupaix

A Time-Interleaved Multimode

A multi-mode delta-sigma (ΔΣ) RF digital-to-analog converter (RF-DAC) is proposed for direct digital-to-RF synthesis. Unlike embedded-mixer ΔΣ RF-DACs which require analog I/Q combining and precise alignment of the local oscillator (LO) and data clock, the proposed circuit is fully digital with only one clock frequency (fS). This architecture eliminates the need for a widely-tuned LO by reconfiguring the ΔΣ modulator (DSM) for a variety of output frequencies, thus making it suitable for software-defined radio. Both a band-pass (BP) and high-pass (HP) DSM are used to synthesize signals at fS/4, fS/2, or 3fS/4. Interleaving is used to reject the first DAC image, doubling the usable bandwidth of the HP DSM while reducing reconstruction filter requirements. The proposed RF-DAC is implemented in 130 nm SiGe BiCMOS. With an fS of 2 GHz, the 0.18 mm2 RF-DAC core consumes 55 mW with output powers of -4.5 dBm, -7.5 dBm, and -13.8 dBm at 0.5 GHz, 1 GHz, and 1.5 GHz, respectively. For the HP DSM, a signal-to-image rejection ratio (SIRR) of 72 dB, an SNR of 54.5 dB over a 50 MHz bandwidth, and an in-band SFDR of 58.5 dB are demonstrated.A multimode delta-sigma (ΔΣ) RF digital-to-analog converter (RF-DAC) is proposed for direct digital-to-RF synthesis. The proposed circuit uses a single clock frequency (f8) and provides a ΔΣ modulator (DSM) that operates in bandpass (BP) and highpass (HP) modes to synthesize signals around f8/4, f8/2, or 3f8/4. The on-chip 14 bit second-order DSM implements an array of 1 bit pipelined subtract functions to generate 3 bit f8 rate RF-DAC input data. Analog interleaving via a second 3 bit DAC is used to reject the first DAC image, simultaneously doubling the usable bandwidth of the HP DSM and increasing the SNR. Calibration circuits are added to the DAC to compensate for amplitude and timing variations. The proposed RF-DAC is implemented in 130 nm SiGe BiCMOS with an area of 0.563 mm2. Measurements at f8 = 2 GHz yield an output power of -0.6 dBm with 76.2 dB signal-to-image-rejection ratio (SIRR), 76.2 dB SFDR over a 100 MHz bandwidth, -80 dBc IM3, -67.2 dB WCDMA ACLR, and -66.4 dBc LTE ACLR. Changing f8 to 3 GHz allows frequencies of 2.25 GHz to be generated with output power of -16.6 dBm, 65.2 dB SFDR, -62 dBc IM3, -59.3 dB WCDMA ACLR, and -59.2 dBc LTE ACLR.

\Delta\Sigma

As line widths in emerging III-V technologies approaching that of modern CMOS, the conception of high performance mixed signal designs such as digital to analog converters (DACs) in the mm-wave space becomes possible. While addressing the speed limitations, candidate III-Vs (InP, GaAs and GaN) are known to suffer from increased switching power consumption, limited device yield and absolute accuracy. CMOS, on the other hand, has the benefit of low-power digital switching, fine resolution and scalability. Recent attempts in marrying the two technologies have been carried out in the DARPA COSMOS program, by integrating III-V type devices with CMOS circuits, so as to exploit the advantages of low-power digital CMOS and high-speed high-power InP. This paper presents some of the challenges as well as prospects in designing record speed and performance DACs in the COSMOS program while contrasting it to that of deeply-scaled CMOS. A multi-phase parallel DAC architecture is leveraged for ultra-wideband synthesis, to improve noise performance and achieve higher information rates. The architectural bounds between CMOS and InP as well as detailed circuit-level analysis of critical block elements will be highlighted.

RF-DAC for Direct Digital-to-RF Synthesis

Simultaneous transmit and receive systems (STAR) are proposed to double the spectral efficiency and enhance spectrum utilization in the traditional microwave band. A major problem is high power self-interference (SI) due to the proximity of the transmit and receive antennas. In this paper, we propose to significantly improve system-level performance using a novel high isolation RF front-end based on collocated Tx/Rx antenna pair(s). Among our improvements, we propose a novel architecture for a STAR system incorporating four stages of self-interference cancellation across the propagation, analog, and digital domains. We aim to attain at least 120dB of total SI cancellation over a >100MHz bandwidth.

Toward Millimeter-Wave DACs: Challenges and Opportunities

This paper proposes a novel control technique for Switched Capacitor Voltage Regulators (SCVRs) that reduces voltage ripple through capacitance reconfiguration. The proposed approach supports wide load range at high efficiency and high power densities, enabling a new class of operation in near-threshold applications. An SCVR design is implemented in 45 nm CMOS SOI process to demonstrate the proposed technique at different load conditions. Simulation results show the design achieving high efficiency (74-80%) across 5-125 mA load range with a high current density of 1.25 A/mm2.

Simultaneous transmit and receive system architecture with four stages of cancellation

Digital-to-analog converters (DACs) are pervasive, critical components for radios and various signal processing systems. Therefore, a myriad of research efforts, covering architectural, circuit, and technological aspects have been made towards improving the performance of DACs. However, the quest to achieve stringent dynamic linearity requirements (>70 dBc SFDR ) over many gigahertz of bandwidth presents grand challenges to designers and high-yield manufacturers. In light of these challenges, various calibration and compensation techniques have evolved over the past two decades to overcome design and process technology variations and limitations.

A fully-integrated switched capacitor voltage regulator for near-threshold applications

Wide-band digital drivers are indispensable for SMPAs (Switched Mode Power Amplifiers) in PWM (Pulse Width Modulation) and PPM (Pulse Position Modulation) applications. This paper presents the design of a wideband RF pre-amplifying buffer, innovated for very low dropout and low power complementary operation in heterojunction technologies affording only depletion type devices. A simple, passive bias level shifting technique is also incorporated to facilitate interfacing the digital modulator in silicon substrate with the PA in III-V wafer. In order to experimentally validate the concepts, the proposed driver is employed for driving an S-band single-ended class-E PA as well as for its differential version, modified to switch over S and C bands, in 130 nm GaAs pHEMT technology. The output powers of the differential amplifier are combined using on-chip transformer balun. Test results of both chips demonstrate that the implemented drivers consume less than 4% of the overall PA efficiencies, wherein the buffer responds linearly to the wideband input pulses when tested alone.

Compensation and Calibration Techniques for Current-Steering DACs

Hardware development of a wideband integrate and dump circuit for a new type of Ultra-wideband (UWB) receiver architecture, called a Transform Domain receiver, is described. For this receiver architecture to be realized, a wide bandwidth Integrate Amplify and Dump (IAD) circuit element is introduced. The IAD interfaces to one of several mixers in a Transform Domain receiver and uses four timeperiods: integration, amplification, conversion, and dump to provide signal projection onto a basis function (the filtering operation) with 80dB of resolution while allowing a low-to-medium dynamic range A/D to perform conversion of basis coefficients. The IAD block design in the IBM8RF process is described as well as configuration and evaluation procedures for the constructed IAD device.

A Wide-Band Complementary Digital Driver for Pulse Modulated Single-Ended and Differential S/C Bands Class-E PAs in 130 nm GaAs Technology

A calibration-free low-power circuit is proposed to reduce the sensitivity of LC VCOs to power supply variations, i.e. supply-pushing. Detailed analysis and design procedure of the proposed circuit are presented and verified by simulations. To illustrate the strength of the proposed technique, the VCO is simulated with and without the proposed circuit. At the highest Kv value of 26 MHz/V, simulation results show 14.5-kHz and 1.01-MHz peak-to-peak deviation from a 1.9-GHz center frequency for a 50-mV supply variation with and without the proposed circuit, respectively. This is equivalent to a supply pushing of 290 kHz/V and 20 MHz/V with and without the proposed circuit, respectively. This represents about 70-times improvement in supply pushing over conventional VCO implementations. In addition, the proposed technique achieves a worst case frequency error of 126 kHz across all process and temperature variations with no calibration. Moreover, the proposed circuit shows negligible effect on the VCO phase noise. At 1.9 GHz, the phase noise of the VCO with the proposed circuit is only degraded by 2.9 dB and 0.1 dB at frequency offsets of 100 kHz and 1 MHz, respectively. The proposed circuit consumes less than 20 μΑ and occupies less than 1.5 % of the total area of the VCO in 90-nm RF CMOS technology.

A wideband integrate, Amplify, and Dump circuit in 0.13um CMOS for Ultra-wideband applications

The push towards mm-wave frequencies has increased the demand for UWB DACs with minimal spurious emissions. At mm-wave, intra-DAC dynamic timing and data errors consume a significant portion of the clock period, degrading SFDR. Previously, NRZ and RZ DACs have been reported with output frequencies up to 27GHz [1–4]. However, their outputs are limited to the first two Nyquist zones, requiring high sample rates which exacerbate dynamic errors. Interleaved DACs allow for synthesis above the first Nyquist zone without increasing the sample rate, although inter-DAC amplitude and timing errors introduce additional spurs at the output that can limit SFDR [5,6]. Alternatively, mixing DACs decouple the sample rate and output frequency, however, they do not deglitch the output, limiting SFDR at high frequency [7]. The multiple return-to-zero (MRZ) architecture mitigates the effects of dynamic errors in the data path, allowing for synthesis up to 9.45GHz with 42dB SFDR [8]. Moreover, the use of R-2R networks achieves binary scaling with the same unit cell current, alleviating switch timing mismatches. Although these techniques improve the intrinsic SFDR of the DAC cells, mismatches in the frequency response of routing interconnects dominate the performance at mm-wave. This is especially critical for the output summing node, which requires an identical amplitude and phase response from each cell to the output. Previously reported DACs used simple structures to combine currents at the output, resulting in large phase and amplitude mismatches. Furthermore, the mm-wave operation of the RZ clock exacerbates the effect of timing errors due to both interconnect and transistor mismatches in the RZ path.

A calibration-free low-power supply-pushing reduction circuit (SPRC) for LC VCOs

A multi-mode delta-sigma (ΔΣ) RF digital-to-analog converter (RF-DAC) is proposed for direct digital-to-RF synthesis. Unlike embedded-mixer ΔΣ RF-DACs which require analog I/Q combining and precise alignment of the local oscillator (LO) and data clock, the proposed circuit is fully digital with only one clock frequency (f S ). This architecture eliminates the need for a widely-tuned LO by reconfiguring the ΔΣ modulator (DSM) for a variety of output frequencies, thus making it suitable for software-defined radio. Both a band-pass (BP) and high-pass (HP) DSM are used to synthesize signals at f S /4, f S /2, or 3f S /4. Interleaving is used to reject the first DAC image, doubling the usable bandwidth of the HP DSM while reducing reconstruction filter requirements. The proposed RF-DAC is implemented in 130 nm SiGe BiCMOS. With an f S of 2 GHz, the 0.18 mm2 RF-DAC core consumes 55 mW with output powers of −4.5 dBm, −7.5 dBm, and −13.8 dBm at 0.5 GHz, 1 GHz, and 1.5 GHz, respectively. For the HP DSM, a signal-to-image rejection ratio (SIRR) of 72 dB, an SNR of 54.5 dB over a 50 MHz bandwidth, and an in-band SFDR of 58.5 dB are demonstrated.