Steven C. Woo

Prototyping a hybrid main memory using a virtual machine monitor

We use a novel virtualization-based approach for computer architecture performance analysis. We present a case study analyzing a hypothetical hybrid main memory, which consists of a first-level DRAM augmented by a 10-100x slower second-level memory. This architecture is motivated by the recent emergence of lower-cost, higher-density, and lower-power alternative memory technologies. To model such a system, we customize a virtual machine monitor (VMM) with delay-simulation and instrumentation code. Benchmarks representing server, technical computing, and desktop productivity workloads are evaluated in virtual machines (VMs). Relative to baseline all-DRAM systems, these workloads experience widely varying performance degradation when run on hybrid main memory systems which have significant amounts of second-level memory.

Pattern generation tools for the development of memory core test patterns for Rambus devices

This paper presents tools that were used in the development of test patterns for Rambus memory devices, Three tools are presented in this paper, Radical, the RL pre-processor, and Rad2MTL. RL and Rad2MTL exploit the capabilities of an executable software model for Rambus DRAMs (Radical) to allow a user to create patterns in a language that supports packet-based protocols and translate the pattern to the Algorithmic Pattern Generator language (MTL) of a memory tester.