Brian Tsang

Prototyping a hybrid main memory using a virtual machine monitor

We use a novel virtualization-based approach for computer architecture performance analysis. We present a case study analyzing a hypothetical hybrid main memory, which consists of a first-level DRAM augmented by a 10-100x slower second-level memory. This architecture is motivated by the recent emergence of lower-cost, higher-density, and lower-power alternative memory technologies. To model such a system, we customize a virtual machine monitor (VMM) with delay-simulation and instrumentation code. Benchmarks representing server, technical computing, and desktop productivity workloads are evaluated in virtual machines (VMs). Relative to baseline all-DRAM systems, these workloads experience widely varying performance degradation when run on hybrid main memory systems which have significant amounts of second-level memory.

A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface

A 800 Mb/s to 3.2 Gb/s memory interface is designed that achieves 30% improved energy efficiency by eliminating idle mode power completely. The link is similar to a standard DDR architecture with the addition of a fast-lock DLL on the memory side that wakes up from 0 mW and locks within 3 clock cycles consuming 24 mW with residual timing error less than 33 mUI. Following initial lock, the DLL operates in a closed loop to compensate for V,T drift consuming 6 mW @ 1.6 GHz including a replica buffer. By incorporating an injection locked oscillator inside the loop, the DLL provides PLL like high frequency input jitter filtering, and corrects ±10% DCD without an additional duty cycle correction loop.

A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching

A dynamic rate adjustable interface is designed a 40-nm LP CMOS process. On-the-fly dynamic rate change is enabled by an all-digital frequency multiplier that detects a reference frequency change, and accordingly provides 4× multiplied clock without any idle time. The clock multiplier, along with matched source synchronous clocking and clock equalization, allows blind reference clock shifting to scale the data rate from 1.6 to 6.4 Gb/s within 6.125ns without idle time or bit errors during transitions. The interface efficiency is 2.6 mW/Gb/s @6.4 Gb/s & 3.4 mW/Gb/s @3.2 Gb/s when using reduced clock swing and external transmitter swing at the reduced data rates.

System design considerations for a 5Gb/s source-synchronous link with common-mode clocking

A 5Gb/s source-synchronous signaling system was developed utilizing embedded common-mode clocking technology to minimize clock distribution delays and to reduce the total pin count. The common-mode clocking scheme forwards the clock on the common mode of the differential data channels. In addition to the signal integrity issues present in differential signaling systems, the embedded common-mode clocking scheme presents additional challenges in system design. By means of impedance control for both common mode and differential mode, careful trace length matching, 5W spacing rule etc, we achieved good signal integrity and the link exhibits good margin. Mode conversion is one of the key issues in the common-mode clocking technology, and it is covered in detail. Measurement results show that the clocking scheme can tolerate −13dB mode conversion on both differential pairs at 5Gb/s.

Low power and low EM emission DRAM memory interface for HD video recording in mobile devices

Next generation processor and DRAM memory for mobile phones are expected to provide the higher bandwidth (BW) necessary for full high definition (HD) video recording. The power consumed by current mobile phones and a camcorder was measured during video capture and extrapolated to estimate the power requirements of 1920×1080p recording at 60 and 120 fps. CMOS process and voltage scaling was then applied to the data. The results show that scaling alone is insufficient to lower the power consumption to within the heat dissipation limit of typical mobile phones. A new, low power DRAM interface is presented to enable handheld devices to record full 3D HD video without overheating the device. This paper also summarizes the impact of the new memory architecture on clock distribution and jitter and the EM emission from the interface. The lack of significant near or far field emission implies that the interface will not disrupt other circuits in the same mobile device when delivering the data rate needed by HD video recording.