Steven E. Butner

Transforming a surgical robot for human telesurgery

This paper discusses the technology and developments behind transformations made to a commercial robotic surgical system, Computer Motion, Inc.s Zeus/spl trade/, in order to make it possible to fully and safely support minimally-invasive human telesurgery performed over very large distances. Because human life is at stake, issues relating to safety, detection of errors, and fail-safe operation are principal in importance. Therefore, it was paramount that all of the safety features of the commercial product Zeus/spl trade/ remained intact during this transformation. This paper discusses the commercial robot and its safety features as well as the real-time communications system added to it as part of Operation Lindbergh, the first transatlantic human telesurgery. Particular attention is paid to the limiting effects of latency. Key techniques developed during this project are discussed, including the need to send the full robot state in each transmitted packet rather than incremental or modal data, thereby treating all telecom problems uniformly as dropped packets. The use of hierarchical design (incorporating Zeus as a drop-in component rather than modifying its internals) allowed the project to focus on the new issues arising due to teleoperation while gaining the robust, error checking, and fail-safe aspects of the design from the use of the unmodified commercial robot. The concept of local mode was created and used during initialization and during communications abnormalities and outages in order to keep the local and remote subsystems active and safely quiescent.

A new architecture for robot control

In this paper we discuss the demanding computational needs of robot control and describe a new computer architecture optimized for such problems. Inverse kinematics and dynamics for 6 degrees of freedom arms are often used as benchmarks to measure controller speed. According to current estimates, the new processor we describe can compute both of these problems, using 32 bit fixed-point operations, in less than 250 microseconds. This is an order of magnitude faster than existing state-of-the-art systems. Such benchmarks only measure a smallportion of the true robot control problem. The issues of interpolation, input/output, and multiple axis synchronization must also be addressed. As robotics becomes more advanced, the need for more compatationally intensive control algorithms (hybrid position/force control, sensory-based control, multiple robot cooperation, etc.) will grow. These now computationally-intractable problems must ultimately be computed in real-time. In this paper, we discuss current progress on a flexible (i.e. programmable) system which is fast enough to approach such problems. The system is targetted to support up to 40 synchronized axes, performing advanced control algorithms with an update rate over 1 KHz.

A real-time system for tele-surgery

Describes a real-time system supporting a tele-surgery application based on the Zeus/sup TM/ system. The application involves performing minimally invasive surgical procedures remotely - i.e. without the surgeon being present in the same room with the patient. Because there is human life at stake, the underlying real-time system must be robust, fail-safe and resilient to communications problems. This paper focuses primarily on the approach taken in communicating between the surgeon-side and patient-side subsystems. In particular, techniques for dealing with the challenges of real-time communications are discussed, e.g. bit errors, packet errors and synchronization. In addition to the control actions and feedback data, several serial data streams are multiplexed, transmitted between one side and the other, demultiplexed, and delivered by the real-time system. These streams have a fundamentally different character from the control actions and feedback values used with the robots. Both types of real-time streams are sent over the same communications link.

The 3DP: a processor architecture for three-dimensional applications

The 3DP (3-Dimensional Processor), a parallel-computing architecture that targets problems that have a 3-D numerical structure and require numerous calculations on 3-D vectors, is described. The 3DP architecture differs from traditional scalar architectures in that it operates directly on vectors. It differs from general parallel architectures in that it can solve problems that predict the behavior of highly coupled systems, and it differs from vector architectures in that it runs efficiently on length-3 vectors. Object-oriented programming on the 3DP and programming the 3DP in C++ are discussed. 3DP performance is reviewed, and the current implementation of the 3DP architecture, as an attached processor that plugs directly into Sun host VMEbus, is described.<<ETX>>

Design and simulation of RIPS: an advanced robot control system

The design and simulation of RIPS, a robotic instruction processing system, are discussed. The authors are building a prototype version of RIPS which will be used as a general research tool to study problems of robot control. The architecture of RIPS is geared for robot control, yet the system is general and fully programmable and does not assume any manipulator characteristics. There is sufficient computing capacity to address any of several important automation problems such as force control, multiple manipulator coordination, or manufacturing cell-level control. Simulations show that using RIPS to control a Stanford manipulator with the computed torque method gives an update rate of 255 mu s. This simulation includes all interprocessor communication as well as the computing time necessary for equation evaluation.<<ETX>>

A fault-tolerant GaAs/CMOS interconnection network for scalable multiprocessors

The design of an interconnection network (ICN) for a scalable multiprocessor system is presented. The tree-structured network (called SHUNT for scalable hierarchical unidirectional network topology) is organized so that it can be scaled not only in width (through the use of bit slicing), but also in number of ports and in data transfer speed. The network is made from three custom chip types: cluster controller, crossbar switch, and network interface. Implementation of the first prototype chips in 2- mu m CMOS is discussed, and the results of detailed circuit simulations for GaAs implementations are given. The network is fault tolerant and is able to detect and correct all single-bit transmission errors. In addition, it can detect failures and reconfigure to work around problems in controllers, port interfaces, or user processors. The network is part of the experimental decoupled computer architect project (DART) currently under study and development. >

GaAs IC fabrication with MOSIS-a user's perspective

Fabrication of GaAs MOSFET digital ICs through the MOS Implementation Service (MOSIS) project. A design strategy for dependable high-speed custom GaAs digital circuits is described. CAD tools adapted for GaAs design are also described. Examples of GaAs IC projects using MOSIS service and the present status of the MOSIS service are examined.<<ETX>>

Evaluation of a prototype VLSI tester

Abstract With the advent and ready accessibility of multi-project fabrication for NMOS and CMOS technologies, creation of custom very large-scale integrated circuits has become commonplace. The functional testing and characterization of the resulting parts requires, in general, an environment that is at least of the same order of complexity as the chip under test. General-purpose test equipment can be found in the industrial marketplace but the cost of such equipment is well into the

Bounding Communication Energy Overhead in Parallel Networks with Power-Delay Scalability

500000 range. Most testers cost over a million dollars. Many costly capabilities (such as per-pin electronics for measuring detailed analog properties of signals) are simply not required for functional prototype testing. This paper describes a general-purpose test stand, designed and built at the Santa Barbara campus of the University of California, to support functional testing and characterization of arbitrary NMOS and CMOS VLSI chips packaged with up to 40 pins. A prototype implementation of the tester is discussed; limitations and planned improvements are also presented.

Architecture and design of a 500-MHz gallium-arsenide processing element for a parallel supercomputer

We propose the energy scalability and power-delay product scalability as new metrics for calculating and estimating boundaries on the energy overhead of parallel processing systems. Because both properties consider network topology and the algorithm to be implemented, they are shown to be effective in predicting the energy scalability of a multiprocessor in the most general case. Power-delay scalability is then shown to provide upper bound and lower bound estimates when analyzing the energy scalability of a multiprocessor while significantly reducing the computational cost of directly calculating the energy scalability. Energy scalability is an effective metric for predicting the energy overhead cost when using a parallel processor versus a single processor. Power-delay scalability is a means for estimating energy scalability on a system when exact calculation may be difficult due to variation in power levels which have become common with dynamic voltage frequency scaling.