Steven Kummerl

Phenomenological Study of the Effect of Microstructural Evolution on the Thermal Fatigue Resistance of Pb-Free Solder Joints

Unlike SnPb solders, the thermal fatigue reliability of the Sn-Ag-Cu (SAC) solders is believed to be influenced significantly by both the initial and evolving microstructures. This paper presents a phenomenological study of the relationship between the initial SAC solder joint microstructure, the evolving microstructure, and the thermal fatigue performance measured by accelerated temperature cycling (ATC). To reflect the board assemblies that are in field use, commercial surface mount components with multiple geometries and materials and from different package assemblers were joined to the board with different lead free SAC alloys. The initial microstructures of the board level solder joints were altered in a variety of ways including: 1) varying the solder joint cooling rate; 2) varying the number of solder reflow exposures; and 3) exposure to different isothermal temperature exposures. In all cases the solder joint microstructure was exposed to one or more of these treatments prior to exposure to temperature cycling. In addition, some of the test boards were exposed to different cycling dwell times to determine if the microstructural evolution that occurred during ATC testing effected the respective characteristic lifetimes of the joints. The microstructural evolution was tracked and characterized with optical metallography and scanning electron microscopy. These results could have practical implications in terms of limiting the ability to develop acceleration factors and effective strain-based models for predicting Pb-free solder joint life.

Increase power density and simplify designs with 3D SiP modules

This paper will discuss volumetric co-design methodology and packaging construction trade-offs for 3D SiP power modules. It will provide more details on SiP eco-system, co-design, construction, materials and circuit topology. Today, designers are demanding an overall form-factor reduction to save board space, increase functionality, and allocate more real estate toward end-user applications - all with less space allocated to power management where not just the X-Y shrink but the 3D volumetric shrink is required. For example, in wearable products, the semiconductor industry has recently seen an increase in the use of system-in-package (SiP) technology for users who want simpler, more flexible designs and need to fulfill challenging space requirements. And we expect to see this trend continue.

Effect of PCB thickness on solder joint reliability of Quad Flat no-lead assembly under Power Cycling and Thermal Cycling

QFN packages gained popularity among the industry due to its low cost, compact size, and excellent thermal electrical performance. Although PCBs are widely used for QFN packages in handheld devices, some customers require it for heavy industrial application demanding thicker PCB. When an electronic device is turned off and then turned on multiple times, it creates a loading condition called power cycling. The die is the only heat source causing non-uniform temperature distribution. The solder joint reliability assessment of Quad Flat no-lead Package (QFN) is done using Finite element analysis (FEA) under two different loads. In this paper, the power cycling and thermal cycling act as a combined load. The reliability assessment is done to check stress distribution on PCB boards and solder joint. The life to failure is determined for QFN package assembly. Also, three different QFN boards were used for analysis and comparison has been done to investigate the impact of thickness and copper content of board on solder joint reliability under power cycling and thermal cycling. The mismatch in coefficient of thermal expansion (CTE) between components used in QFN and the non-uniform temperature distribution makes the package deform. Modeling of life prediction is usually conducted for Accelerated Thermal Cycling (ATC) condition, which assumes uniform temperature throughout the assembly. An assembly is also subjected to Power Cycling i.e. non-uniform temperature with the chip as the only source of heat generation. This work shows the performance of QFN package assembly under thermal and power cycle in combination and the stress distribution and plastic work for the package. The layered model analysis was done to investigate the impact of the FR4 layer and copper content in the PCB on the solder joint reliability. The comparative study between lumped and layered model has also done under power cycling and thermal cycling.

Failure mechanisms of boards in a thin wafer level chip scale package

Various studies have been conducted to study the effect of varying board thickness on thermo-mechanical reliability of BGA packages. Wafer level chip scale packages (WLCSP) have also been studied in this regard to determine the effect of PCB build-up thickness on the solder joint reliability [1]. The studies clearly demonstrate that the thinner Printed Circuit Boards (PCBs) result in longer thermo-mechanical fatigue life of solder joints for BGA. With the literature and past trends supporting the idea of thinner boards, manufacturer opted to move forward by decreasing the thickness of their PCBs to improve the reliability of their packages. The thickness was reduced from 1mm to 0.7mm by decreasing the thicknesses of individual layers and keeping the total number of layers constant. When subjected to thermal cycling, it was observed that 0.7mm board was failing earlier than the 1mm board. Since this behavior of a WLCSP contrasts with the past trends, it required extensive study to determine and understand the pre-mature physics of failure/causality of failure in 0.7mm board. In this paper, an effort is made to understand the mechanism which is causing an early failure in the thinner board. The effect of number & thicknesses of core layers, prepregs and Cu layers in the board has been studied through material characterization of both 1mm and 0.7mm boards. Further, a design optimization account has also been presented to improve the thermo-mechanical reliability of this package.

Mechanical characterization of RCC and FR4 laminated PCBs and assessment of their board level reliability

The role of electronic packaging is becoming more important and now constitute a much bigger percentage of the development of package with high evolution due to strong and competing demands for increased functionality and performance, further miniaturization, heightened reliability, and lower costs. Various types of packages like BGA and Quad Flat No-Lead (QFN) are widely used. Ball Grid Array package was developed out of the need to have a more robust and convenient package for integrated circuits with large numbers of interconnects. Moreover, BGA uses efficient board space, improved thermal and electrical performance, reduced package thickness and improved reworkability resulting from larger pad size. The different layers with different material properties inside the PCB (Printed Circuit board) make the PCB highly orthotopic. Additionally, prepreg materials are viscoelastic and they provide some sort of stress relaxation and creep characteristics. Currently, there are two types of boards that are used with BGA packages. One of the types has RCC film as the uppermost and lowermost prepreg substrate while the second type has FR4 film as the uppermost and lowermost prepreg substrate. By using Dynamic Mechanical Analyzer (DMA), time and temperature-dependent viscoelastic properties of the board are obtained. Using Thermomechanical Analyzer (TMA), Coefficient of Thermal Expansion (CTEs) of the boards are obtained. In summary, in this study, the mechanical characterization of BGA PCBs with FR4 and RCC is presented along with the thermal cycling simulation results from ANSYS and the reliability of two types of boards were compared. The computational analysis includes lumped and layered model for detail analysis. The Volume averaging technique is implemented to calculate the strain energy density. The Critical solder joint is determined from the static structural analysis under thermal loading.

Solder ball reliability assessment of WLCSP — Power cycling versus thermal cycling

Failure analysis and its effects are major reliability concerns in electronic packaging. More accurate fatigue life prediction can be obtained after the consideration of all affecting loads on the electronic devices. When an electronic device is turned off and then turned on multiple times, it creates a loading condition called power cycling. WLCSP use a package technology at the wafer-level, which is an extension of the wafer fab process where the final device is a die with an array pattern of the solder interconnects. The die is the heat source causing non-uniform temperature distribution. The solder ball reliability assessment of wafer level chip scale package (WLCSP) is done through Finite element analysis (FEA) under two different loads. In this paper, the power cycling is done to check its solder ball reliability by estimating stresses and failure life cycles. The mismatch in coefficient of thermal expansion (CTE) between components used in WLCSP and the non-uniform temperature distribution makes the package deform resulting in thermal stresses. Cross-sectioning of the PCB was also performed and it has been observed that the life of any assembly also depends on the copper content in the PCB board. This study shows the contradictory results from the literature, i.e. the reliability of thinner board will be more compared to thicker boards. The thermal cycling test is also done on the same package to compare the effect of power cycle and thermal cycle. For more comparative analysis, accelerated thermal cycling (ATC) is performed on WLCSP. The internal heat generation from power cycling shows more failure and more accurate results compared to thermal cycling.