Edward W. Kiewra

A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications

The first sub-100nm technology that allows the monolithic integration of optical modulators and germanium photodetectors as features into a current 90nm base high-performance logic technology node is demonstrated. The resulting 90nm CMOS-integrated Nano-Photonics technology node is optimized for analog functionality to yield power-efficient single-die multichannel wavelength-mulitplexed 25Gbps transceivers.

Monolithic Silicon Integration of Scaled Photonic Switch Fabrics, CMOS Logic, and Device Driver Circuits

We demonstrate 4 × 4 and 8 × 8 switch fabrics in multistage topologies based on 2 × 2 Mach-Zehnder interferometer switching elements. These fabrics are integrated onto a single chip with digital CMOS logic, device drivers, thermo-optic phase tuners, and electro-optic phase modulators using IBMs 90 nm silicon integrated nanophotonics technology. We show that the various switch-and-driver systems are capable of delivering nanosecond-scale reconfiguration times, low crosstalk, compact footprints, low power dissipations, and broad spectral bandwidths. Moreover, we validate the dynamic reconfigurability of the switch fabric changing the state of the fabric using time slots with sub-100-ns durations. We further verify the integrity of high-speed data transfers under such dynamic operation. This chip-scale switching system technology may provide a compelling solution to replace some routing functionality currently implemented as bandwidth- and power-limited electronic switch chips in high-performance computing systems.

Inversion mode n-channel GaAs field effect transistor with high-k/metal gate

Highly effective passivation of GaAs surface is achieved by a thin amorphous Si (a-Si) cap, deposited by plasma enhanced chemical vapor deposition method. Capacitance voltage measurements show that carrier accumulation or inversion layer is readily formed in response to an applied electrical field when GaAs is passivated with a-Si. High performance inversion mode n-channel GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with an a-Si/high-k/metal gate stack. Drain current in saturation region of 220mA∕mm with a mobility of 885cm2∕Vs were obtained at a gate overdrive voltage of 3.25V in MOSFETs with 5μm gate length.

High-Performance

Long and short buried-channel In0.7Ga0.3As MOSFETs with and without alpha-Si passivation are demonstrated. Devices with alpha-Si passivation show much higher transconductance and an effective peak mobility of 3810 cm2/ V middots. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 muA/mum at Vg - Vt = 1.6 V and peak transconductance of 715 muS/mum. In addition, the virtual source velocity extracted from the short-channel devices is 1.4-1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance In0.7Ga0.3 As-channel MOSFETs passivated by an alpha -Si layer are promising candidates for advanced post-Si CMOS applications.

\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}

We present a 16-Gb/s transmitter composed of a stacked voltage-mode CMOS driver and periodic-loaded reverse biased pn junction Mach-Zehnder modulator. The transmitter shows 9-dB extinction ratio and 10.3-pJ/bit power consumption and operates with 1.3 μm light. Penalties as low as 0.5 dB were seen as compared to a 25-Gb/s LiNbO3 transmitter with both a monolithic metal-semiconductor-metal receiver and a reference receiver at 16-Gb/s operation. We also present an analytic expression for relative transmitter penalty (RTP), which allows one to quickly assess the system impact of design parameters such as peak-to-peak modulator drive voltage, modulator figure of merit, and transmitter extinction ratio to determine the circumstances under which a stacked CMOS cascode driver is desirable.

-Channel MOSFETs With High-

A monolithically-integrated germanium receiver is fabricated in the IBMs newly established 90nm CMOS-integrated nanophotonics technology node. Technology is promising for cost-effective 10Gbps to 28Gbps optical communications links operating within extended temperature range up to 95°C.

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We demonstrate in a single chip a complete multiport photonic switching system using IBM 90-nm photonics-enabled CMOS. The system includes CMOS logic, switch drivers, multistage 4×4 and 8×8 photonic switch fabrics, and thermo-optic phase tuners.

Gate Dielectrics and

Sub-100 nm short-channel In0.7Ga0.3As MOSFETs are demonstrated for both depletion- and enhancement-mode devices. High current of 960 muA/mum and record transconductance of 793 muS/mum have been achieved. Scaling behavior is investigated experimentally down to 80 nm for the first time in III-V MOSFETs. Good scaling behavior is observed for on-state current, transconductance, as well as the virtual source velocity.

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We propose a coupling-modulated microring in an add-drop configuration for binary phase-shift keying (BPSK), where data is encoded as 0 and π radian phase-shifts on the optical carrier. The device uses the π radian phase-flip across the zero coupling point in a 2 × 2 Mach-Zehnder interferometer coupler to produce the modulation. The coupling-modulated microring combines the drive power reduction of resonant modulators with the digital phase response of Mach-Zehnder BPSK modulators. A proof-of-concept device was demonstrated in silicon-on-insulator, showing differential binary phase-shift keying operation at 5 and 10 Gb/s.

-Si Passivation

We present a monolithic CMOS-integrated nanophotonic transmitter with a link sensitivity comparable with a 25-Gb/s commercial reference transmitter. Our CMOS transmitter shows error-free operation up to 32 Gb/s, and exhibits a 4.8-dB extinction ratio and 4.9-dB insertion loss at 25 Gb/s.