Steven P. Ostrander

Internal Thermal Management of IBM P-Server Large Format Multi-Chip Modules Utilizing Small Gap Technology

The large Multi-Chip Modules (MCM) used in the IBM p-Server computer systems, and their predecessors, have required rather unique cooling solutions and module hardware designs in order to meet the thermal, mechanical and reliability requirements placed on the package. The module internal thermal solution has evolved from a spring-loaded metal contact technology to a thermal compound based design using a novel gap adjustment technology employing a soldered conduction component. This current MCM makes use of a novel technology called Small Gap Technology (SGT). This technique makes it possible to control thermal compound interface thicknesses or gaps to a very tight tolerance from chip-to-chip and module-to-module. Heat flux values that have been handled vary from approximately 20 to 53 W/cm2 depending on the type of chip and the system performance level. Even higher heat fluxes have been projected for next generation products. The hardware and processing techniques employed to manufacture these modules are quite unique. These products are typically on the order of 100mm chip carrier size or 140mm overall module footprint on a side (approximately 90 cm2 of carrier area) and contain 8 chips and numerous discrete devices. The process fixturing and equipment must be able to handle the relatively large thermal mass of the components. The sequence of processing steps must take into account limitations on the material properties of the various module components. This paper will describe the SGT thermal management solution. The hardware and process employed to make the gap adjustments and the thermal interface material used in these high heat flux applications will be discussed. In addition, supporting thermal/mechanical modelling, thermal performance data and reliability data will be presented.Copyright

Correlation of Dielectric Film Flex Fatigue Resistance and Package Resin Cracking Failure

Resin cracking is a common failure mechanism in electronic packaging using organic chip carrier. Chip carrier made of organic material has been industry standard for the past decade as they provide significant advantages over the ceramic dielectric-based predecessors in manufacturing cost and electrical performance. However, the CTE mismatch between the silicon chip and the organic laminate leads to substantial stress in the laminate particularly at the outmost fiber. Such stress when combined with the temperature fluctuation in field operation, causes low cycle fatigue in dielectric layer and eventually impairs the circuits in the laminate, which is known as dielectric resin cracking failure. During the evolution of organic laminate technology, the demands for high speed transmission drives the need for material with low dielectric loss, which usually is associated with low ductility and in turn makes dielectric resin cracking an even greater concern. A cost effective evaluation method for testing the resin cracking robustness of an interested material before building expensive laminate is therefore critical. This paper focuses on correlation of raw dielectric film material properties and the reliability performance of the corresponding electronic package. A fabricated in-house strain controlled fatigue testing machine will be introduced. The fatigue life vs strain of a typical dielectric material will be discussed. A flip chip package using this dielectric material will be described. Its resin cracking failure rate subjected to thermal cycling stress with various delta T will be illustrated. The thermal-mechanical modeling methodology will be outlined and verification of simulations with experimental results will be presented. A predictive model for correlation of dry film flex fatigue life and the corresponding resin cracking risk in a flip chip package will be proposed.