Edmund Blackshear

Flip chip assembly method employing differential heating/cooling for large dies with coreless substrates

In this work, differential heating/cooling chip join process was developed for coreless flip chip packaging to minimize warpage change of coreless substrates during the bonding process. A chip was vacuumed to a bonder head and a coreless substrate was vacuumed on a base plate and they were held at different elevated temperatures during the bonding process. The temperature difference provides a substantially matched thermal expansion between the silicon chip and the coreless substrate. This minimizes stress induced by low coefficient of thermal expansion (CTE) mismatch during flip chip assembly. Both thermal and mechanical modeling were performed to provide more detailed information about the temperature distributions and warpage levels for all package components during the chip join process. Mechanical modeling of the chip join process confirmed that by implementing differential heating/cooling chip join process the stresses within the solder bumps can be reduced by more than 20% and the stresses in the low-k layers within the chip can be reduced by more than 25%. Our evaluations used semiconductor chips with a known low-k dielectric and SnAg solder bumps. The size of the test chip was approximately 19 mm × 19 mm with less than 150 μm pitch. The coreless substrate was 55 mm × 55 mm with 8+1 layers. The samples were bonded with an optimized differential heating/cooling chip join process. The experimental results showed that there were no C4 (Controlled Collapsible Chip Connection) bumps bridging, non-wets, nor low-k delamination in the large die with coreless package. Reliability data showed no failures in any of the tested modules.

Advanced laminate carrier module warpage considerations for 32nm pb-free, FC PBGA package design and assembly

The trend in large body, high performance integrated circuit packaging for the 32 nm semiconductor node and beyond is towards low dielectric loss to enable high bandwidth / low loss channels, and low thermal expansion to protect fragile, ultra-low dielectric constant (k) chip dielectric materials from differential expansion stress. A low coefficient of thermal expansion (CTE), low dielectric loss laminate composite was developed using industry standard Sequential Build Up (SBU) fabrication techniques and novel laminate materials. This laminate technology was used in assembly of a Flip Chip Plastic Ball Grid Array (FC PBGA) module including a silicon test structure developed for 32 nm Custom Logic development. The same silicon test structure and laminate design were also used to fabricate modules using conventional high volume laminate materials. Various laminate physical parameters including composite CTE were determined. The warpage shape of each laminate was initially characterized at room temperature, and over the temperature range from 25°C to 240°C. Warpage of critical package features was measured and tracked throughout the various steps of the lead free flip chip module assembly process for multiple laminate cross sections, core and buildup materials. A quantity of assemblies of each type was built and measured, data is reported. Advantages and disadvantages of each laminate module type and implications for robust package assembly as evidenced by these results are discussed.

Electromigration study on the interconnects of high density power modules

As the current carrying requirements increase to power the loads within server equipment, the interconnect system throughout the complete power delivery path becomes a very critical element to the overall system reliability. In addition to the electrical attributes of the interconnect, the mechanical and electro-chemical nature of the interconnect system are also key. As the voltage delivered to server microprocessors continue to drop to sub 1 V levels, the high amperage demand increases the current densities on the interconnects including those within power module packages. These high current densities, which can be on the order of 104 A/cm2, may create long term reliability concerns due to electromigration phenomenon on the interconnect such as the internal fine-pitch ball grid array (BGA) interconnects used within power modules. This paper presents the results of a study which was performed to understand the possible electromigration impacts to the reliability of the BGA interconnects of high density power modules in real-world server applications.