Frank L. Pompeo

An advanced multichip module (MCM) for high-performance UNIX servers

In 2001, IBM delivered to the marketplace a high-performance UNIX?®-class eServer based on a four-chip multichip module (MCM) code named Regatta. This MCM supports four POWER4 chips, each with 170 million transistors, which utilize the IBM advanced copper back-end interconnect technology. Each chip is attached to the MCM through 7018 flip-chip solder connections. The MCM, fabricated using the IBM high-performance glass-ceramic technology, features 1.7 million internal copper vias and high-density top-surface contact pad arrays with 100-?µm pads on 200-?µm centers. Interconnections between chips on the MCM and interconnections to the board for power distribution and MCM-to-MCM communication are provided by 190 meters of co-sintered copper wiring. Additionally, the 5100 off-module connections on the bottom side of the MCM are fabricated at a 1-mm pitch and connected to the board through the use of a novel land grid array technology, thus enabling a compact 85-mm ?? 85-mm module footprint that enables 8- to 32-way systems with processors operating at 1.1 GHz or 1.3 GHz. The MCM also incorporates advanced thermal solutions that enable 156 W of cooling per chip. This paper presents a detailed overview of the fabrication, assembly, testing, and reliability qualification of this advanced MCM technology.

Differential heating/cooling chip joining method to prevent chip package interaction issue in large die with ultra low-k technology

A differential heating/cooling chip join method was developed for Pb-free flip chip packaging of ultra low-k (ULK) technology Si chips on organic substrates to prevent Chip-Package Interaction (CPI) - related damage upon chip joining. A chip was mounted to a bonder head and a substrate was located on a base plate and they were held at different elevated temperatures during the bonding process. The temperature difference between the Si chip and the organic substrate during assembly provides a substantially matched thermal expansion and minimizes stress induced by coefficient of thermal expansion (CTE) mismatch. From the modeling study, it was confirmed that chip warpage, Controlled Collapse Chip Connection (C4) stresses/strains, and ULK stresses decreased significantly by differential heating/cooling chip join method, with further improvement noted as the substrate temperature was decreased during the bonding process. X-ray, scanning electron microscope (SEM) and C-mode scanning acoustic microscope (C-SAM) were used to examine the defects after flip chip assembly. Noncontact white light reflectometry was also used to measure the warpage shape of the assembled silicon chip and the organic substrate. Observation under C-SAM indicated that fractures in the ULK layers were dramatically reduced by the differential heating/cooling chip joining process compared to the conventional reflow process. Non-destructive X-ray images indicated there were no solder bridging in any area of the chip interconnects. The experimental results showed that the differential heating/cooling chip join process can effectively reduce fractures in the ULK layers and prevent C4 bump bridging in a large die package with low-K dielectric constant device integration and high Ag content solder bumps.

Phase change materials as a viable thermal interface material for high-power electronic applications

Phase change materials (PCMs) are an attractive alternative to thermal greases/pads. While their thermal conductivity is not as good as greases, they are more manufacturable. This paper reports on evaluation of PCMs for high power electronic applications. Conductivity measurements were carried out for several OEM PCMs. In addition experiments were carried out to determine process parameters (to attain target thermal impedance). A few candidates were then evaluated in a single chip module, under different environmental stresses and the results are presented here. The design concept was then extended to an MCM test vehicle and two candidate PCMs were evaluated. Differences in the reliability performance between SCM and MCM form factor are explained.

Advanced laminate carrier module warpage considerations for 32nm pb-free, FC PBGA package design and assembly

The trend in large body, high performance integrated circuit packaging for the 32 nm semiconductor node and beyond is towards low dielectric loss to enable high bandwidth / low loss channels, and low thermal expansion to protect fragile, ultra-low dielectric constant (k) chip dielectric materials from differential expansion stress. A low coefficient of thermal expansion (CTE), low dielectric loss laminate composite was developed using industry standard Sequential Build Up (SBU) fabrication techniques and novel laminate materials. This laminate technology was used in assembly of a Flip Chip Plastic Ball Grid Array (FC PBGA) module including a silicon test structure developed for 32 nm Custom Logic development. The same silicon test structure and laminate design were also used to fabricate modules using conventional high volume laminate materials. Various laminate physical parameters including composite CTE were determined. The warpage shape of each laminate was initially characterized at room temperature, and over the temperature range from 25°C to 240°C. Warpage of critical package features was measured and tracked throughout the various steps of the lead free flip chip module assembly process for multiple laminate cross sections, core and buildup materials. A quantity of assemblies of each type was built and measured, data is reported. Advantages and disadvantages of each laminate module type and implications for robust package assembly as evidenced by these results are discussed.

Multi-chip package thermal management of IBM z-server systems

The recently announced IBM z9 server system presents unique cooling requirements from a packaging perspective. Cooling has to be achieved for sixteen chips mounted on a common glass ceramic chip carrier. Eight of the sixteen chips dissipate significant power. A recently described small gap technology (SGT) is used to attain customized chip to cap gaps. An advanced thermal compound (ATC) is used as the interface between the chips and the cap. The package thermal and mechanical design is first described. Design optimization is achieved by detailed finite element thermo-mechanical modeling. The complex encapsulation process to attain the correct chip to hat ATC gaps is outlined. Verification of the ATC gaps is an integral part of the assembly process. The reliability qualification is then discussed. Issues found during the qualification were the structural fragility of the glass ceramic chip carrier flange and ATC thermal degradation. The structural robustness of the chip carrier was improved by modifying its design. ATC degradation is quantitatively related to the shear strain

An effective method for full solder intermetallic compound formation and Kirkendall void control in Sn-base solder micro-joints

Kirkendall voids are defects that significantly reduce the mechanical properties as well as the electromigration (EM) resistance of Sn base solder joints. In this paper, an effective method was utilized in the micro-joints to fully convert Sn-Ag solder into intermetallics (IMC), to suppress the formation of Kirkendall voids. Silicon chip samples with Sn-based micro-joints (30um diameter) and Cu pillar structures were fabricated with different joint layer metallurgy to investigate the impact of the Cu pillar thicknesses, solder amount and with or without Ni layer on the IMC formation behavior. Both IMC growth and Kirkendall evolution was studied under high temperature storage (HTS) at 150C for 500 hours and 1000 hours. A process called short term 2nd reflow was used to enhance the Sn-Ag solder to IMC conversion. For comparison, Si chip samples with more typical joint diameter (82um) were also fabricated. We found the 2nd reflow process fully converted Sn-Ag solder into IMC in the micro-joint samples. However, the 2nd reflow process was not practical for samples with larger solder (82um diameter) volume, since this process consumed the Ni layer under bump metallurgy on the bottom side.

Failure analysis of thermal degradation of TIM during power cycling

This paper discusses a thermal reliability testing experiment and failure analysis (FA) in 32nm SOI Si technology chip packages. Thermal performance of the TIM materials is monitored and physical failure analysis is performed on test vehicle packages post thermal reliability test. Thermomechanical modeling is conducted for different test conditions. TIM thermal degradation is observed at the chip center area in the batch of samples post power cycling (PC) test, while the TIM performance remains normal in the other batch of samples post thermal aging (TA) test. Physical FA findings after TIM bond line thickness measurement (at the chip corners and chip center) and unlidding to inspect the TIM surface morphology confirmed the failure mode is TIM to chip tearing. Finite element modeling results indicate significant difference of stress status in TIM and sealband adhesive between PC and TA test. The TIM experiences compressive stress during PC test, while it is in tensile stress during TA test.

Hermetic Encapsulation Technique Developed for the IBM Z-Server Multi-Chip Module

The large MCM developed to package the main processor unit used in the IBM z9 Server makes use of a novel sealing design that imparts many desirable characteristics to the module assembly process, performance and reliability. These packages consist of a large ceramic chip carrier encapsulated using a copper cooling cap and a metal sealing ring. The sealing technique not only provides the hermetic environment needed to protect the non-underfilled devices contained within the module, but also allows for easy rework of the assembly. The seal used can withstand the thermally induced stresses and strains driven by the thermal expansion coefficient mismatch between the carrier and the cap. Depending on the system requirements or application, it can do this and reliably maintain the level of hermeticity needed to protect the encapsulated devices over a thousand or more thermal cycles. In addition to this, the seal and module design must compensate for mechanical tolerances of the carrier and devices that affect the assembled condition of the module. In the z-Server module design these considerations, as well as thermal performance factors, are all taken into account. This paper will cover the various aspects of the module design, focusing on the novel application of the hermetic seal employed. The seal will be described and its design parameters will be discussed. Seal, component and module level qualification testing that is performed to insure that the assembly meets the package reliability requirements will be presented.Copyright

A Novel Failure Analysis Technique for Semiconductor Packaging by Xenon Difluoride Gas

Defect isolation and failure analysis is a key factor that drive development and manufacturing yield improvements in semiconductor packaging industry. From a manufacturing point of view, ensuring adequate package reliability is becoming more challenging due to increasing packaging complexity and a more pronounced impact from material physical property mismatch among packaging materials and components. The task of isolating defects and finding root cause is further complicated by ever shrinking feature sizes within the device and/or package, already approaching the nanometer range in contemporary semiconductor packages. Conventional failure analysis techniques such as physical cross sectioning or micro-cutting using focused ion beams(FIB) are sometimes no longer sufficient to find these defects. Both physical cross section and FIB are only capable of exposing the defect in two dimensions (x and y directions), which makes pinpointing the defect in depth, i.e., the z direction, extremely difficult when dealing defects with micron and submicron size. Additional complications are many times introduced during conventional sample preparation, which can introduce undesirable artifacts associated with the module and/or device depackaging. These artifacts may mask the true defects, or lead to misinterpretation of the true cause of failure. In this work, it has been determined that a three-dimensional failure analysis method is critical for finding some defects in silicon packages. For example, xenon difluoride (XeF2) has excellent selectivity to silicon and provides efficient material removal by chemical reaction, generating gaseous by-products that can be readily exhausted [1]. Furthermore, XeF2 has very little reaction with non-silicon materials, such as SiO2, and the metals and polymers commonly used in semiconductor devices and packages. This paper reports the application of XeF2 as an effective failure analysis technique to reveal defects in silicon packages. The mechanism of selective reaction between XeF2 and Si is discussed and key design features of the failure analysis tool are presented. The paper also highlights a few case studies which advantageously utilize XeF2 etching to expose defects. XeF2 was especially effective in detecting the source of electrical leakage in 3D packages having Through Silicon Via (TSV) structures. Due to its high etching selectivity to silicon, the leakage area in electrically failing samples was found to be due to damage of the TSV liner (passivation layer material) and further analysis reveals a three dimensional view of the TSV defect. With the addition of XeF2 etching, further characterization of defects by traditional methods such as FIB micro cutting also becomes more practical. The work suggests that a wider application of Si removal via XeF2 can be achieved by combining mechanical milling of bulk silicon followed by a final, low stress, silicon removal by XeF2 etching.

A high performance Multi Component Carrier with Chip Scale Package

In this paper, we discuss the design of a four (4) chip Multi Component Carrier (MCC) package and feasibility for use in high-end server/mainframe applications. A new class of organic, Chip Scale Package (CSP) and associated design ground rules were created based on a low, coefficient of thermal expansion (CTE) organic material, in addition to the CSP form factor. Micro Ball Grid Array (BGA) is used to connect the CSP to a daughter card assembly to form the MCC package structure. The low CTE organic substrate significantly reduces the internal stress that arises from the chip to substrate bond and assembly process, which enhances the yield and reliability of the CSP and the entire MCC structure. Numerical simulation using the finite element method (FEM) has been conducted to evaluate and optimize the lid design of the MCC package in order to ensure reliable lid to package operation during assembly and field thermal excursions. Thermal and mechanical solutions with various combinations of geometric design are discussed.