Jeyanandh Paramesh

A four-antenna receiver in 90-nm CMOS for beamforming and spatial diversity

A fully integrated four-channel multi-antenna receiver intended for beamforming and spatial diversity applications is presented. It can also be used as a low-power area-efficient range extender for spatially multiplexed multi-antenna systems that are poised to become mainstream in the near future. Implemented in a 90-nm CMOS technology, each channel weights its input signal by a complex weight with full 360/spl deg/ phase shift programmability using vector combinations of variable-gain amplifiers, thus obviating the need for expensive phase shifters. The chip consumes 140 mW from a single 1.4-V supply and achieves 12 dB of array gain with all four channels activated and >20 dB direction-of-arrival-dependent interference rejection.

A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion

A linear Doherty amplifier is presented. The design reduces AM-PM distortion by optimizing the device-size ratio of the carrier and peak amplifiers to cancel each others phase variation. Consequently, this design achieves both good linearity and high backed-off efficiency associated with the Doherty technique, making it suitable for systems with large peak-to-average power ratio (WLAN, WiMAX, etc.). The fully integrated design has on-chip quadrature hybrid coupler, impedance transformer, and output matching networks. The experimental 90-nm CMOS prototype operating at 3.65 GHz achieves 12.5% power-added efficiency (PAE) at 6 dB back-off, while exceeding IEEE 802.11a -25 dB error vector magnitude (EVM) linearity requirement (using 1.55-V supply). A 28.9 dBm maximum Psat is achieved with 39% PAE (using 1.85-V supply). The active die area is 1.2 mm/sup 2/.

Three-Terminal Probe Reconfigurable Phase-Change Material Switches

We present the realization of a novel three-terminal electronic switch using phase-change (PC) chalcogenide material. This device subdivides a single PC switch into a parallel array of three-terminal subvias which are addressed with atomic-force-microscopy cantilever probes. This subdivision reduces the required switching current to acceptable levels. Vias of Ge50Sb50 are demonstrated in this switch topology and are switched between high- and low-resistance states. The vias show an off/on resistance ratio of approximately 100×, which can be applied in radio-frequency switching applications. This dynamic range is 10× less than that observed in sheet films of this material, with the main loss being a reduction in resistivity between the sheet-film off-state and the device off-state. The device off -state resistivity is similar in the as-fabricated state and the reamorphized state.

Use of sigma-delta modulation to control EMI from switch-mode power supplies

Conducted electromagnetic interference (EMI) is a major cause of concern in switch-mode power supplies (SMPS) which commonly use standard pulsewidth modulation (PWM). In this paper, sigma-delta (/spl Sigma//spl Delta/) modulation is proposed as an alternative switching technique to reduce conducted EMI from SMPS. The result of using /spl Sigma//spl Delta/ modulation is a spread in the spectrum of the conducted emissions so that large concentrations of power at discrete frequencies are avoided. Experimental time-domain waveforms and spectra of the switching function of first-order and second-order /spl Sigma//spl Delta/ modulators are presented to prove the viability of the scheme for EMI mitigation. These modulators are then applied to a DC-DC power converter in an off-the-shelf computer power supply and experimental results show a reduction of roughly 5-10 dB/spl mu/V in EMI emissions over standard PWM modulators.

A phase-change via-reconfigurable on-chip inductor

This paper describes a new approach to the realization of reconfigurable CMOS-compatible RF inductors using programmable vias made from phase-change (PC) materials. Reversible reconfiguration of a custom-fabricated inductor prototype is demonstrated using voltage pulses to transform (by Joule heating) the PC switch between crystalline (ON) and amorphous (OFF) states. The RF performance shows an inductance of 1.9 (0.9) nH at 2 (5) GHz with quality factor (Q) of 12.4 (5.8) in the OFF (ON) state.

A 1.4V 5GHz four-antenna Cartesian-combining receiver in 90nm CMOS for beamforming and spatial diversity applications

A 90nm CMOS four-channel analog beamforming receiver draws 140mW at 1.4V and achieves 6dB SNR improvement with 360/spl deg/ look-angle coverage and 20dB interference cancellation. Vector combinations of programmable gain elements eliminate the need for explicit phase shifters. The analog combining technique is also useful as a low-power range extender/interference canceller in conjunction with spatial-multiplexing MIMO.

A Phase-Change Via-Reconfigurable CMOS

This paper demonstrates the efficacy of phase-change (PC) vias in reconfiguring RF front-end circuits for multiband/multi-standard operation. Constructed using two series-connected (SC) GeTe vias, a PC switch can be reversibly transformed between a high ROFF state and a low RON state within 1 μs. Using such PC switches to switch the inductor in a resonator, two LC voltage-controlled oscillators (VCOs) based on: 1) a SC and 2) a coupling-controlled (CC) resonator are developed. Designed and fabricated in 0.13- μm CMOS in conjunction with an in-house GeTe process, the VCOs can switch their operating frequency over widely separated bands. Wide tuning ranges of 2.89-4.23/(4.93-7.79) and 4.80-8.53/(5.28-10.20) GHz were achieved in the off/on state for the SC/(CC) VCOs. The measured phase noise over the entire tuning range was lower than -103.4 and -102.7 dBc/Hz, at a 1-MHz offset frequency, respectively.

LC

Several fully-integrated multi-stage lumped-element quadrature hybrids that enhance bandwidth, amplitude and phase accuracies, and robustness are presented, and a fully-integrated double-quadrature heterodyne receiver front-end that uses two-stage Lange/Lange couplers is described. The Lange/Lange cascade exploits the inherent wide bandwidth characteristic of the Lange hybrid and enables a robust design using a relatively low transformer coupling coefficient. The measured image-rejection ratio is > 55 dB over a 200 MHz bandwidth centered around 5.25 GHz without any tuning, trimming, or calibration; the front-end features 23.5 dB gain, -79 dBm sensitivity, 5.6 dB SSB NF,-7 dBm IIP3, -18 dB S11 and a 1 mm times 2 mm die area in 0.18 mum CMOS.

VCO

Improvements to the GeTe inline phase-change switch (IPCS) technology have resulted in a record-performing radio-frequency (RF) switch. An ON-state resistance of 0.9 Ω (0.027 Ω·mm) with an OFF-state capacitance and resistance of 14.1 fF and 30 kΩ, respectively, were measured, resulting in a calculated switch cutoff frequency (Fco) of 12.5 THz. This represents the highest reported Fco achieved with chalcogenide switches to date. The threshold voltage (Vth) for these devices was measured at 3V and the measured third-order intercept point (TOI) was 72 dBm. Single-pole, single-throw (SPST) switches were fabricated, with a measured insertion loss less than 0.15 dB in the ON-state, and 15dB isolation in the OFF-state at 18 GHz. Single-pole, double-throw (SPDT) switches were fabricated using a complete backside process with through-substrate vias, with a measured insertion loss 0.25 dB, and 35dB isolation.

Integrated Quadrature Couplers and Their Application in Image-Reject Receivers

This paper presents a four-element phased-array receiver which achieves 38% fractional bandwidth around 55 GHz. Baseband phase-shifting is employed to eliminate wideband phase-shifters, power dividers, and quadrature splitters operating at millimeter-wave frequencies. Antenna weighting and combining are accomplished using a highly digital Cartesian phase-shifter and current summation, respectively. Transformer-coupling techniques are introduced in the LNA to simultaneously achieve wide bandwidth, reduced noise figure, gain boosting and neutralization. Cascode-free and folded topologies are used throughout to enable operation from a scalable supply voltage. To overcome challenges associated with wideband LO distribution, the LO network employs multiconductor transmission lines to distribute four-phase LO signals. The LO distribution network is absorbed into the LO buffers and terminated by distributed LC loads near the I/Q mixers in each phased-array element. The phased-array receiver is fabricated in a 45 nm SOI CMOS process and achieves 26.2 dB (20.2 dB) of element gain over 21 GHz (19 GHz) of 3 dB bandwidth with 5.5 dB/9.8 dB (7.7 dB/12 dB) minimum/maximum NF while dissipating 30 mW/element (14 mW/element) from a 1.1 V (0.6 V) supply voltage. The worst case -1 dB (input) compression is -28 dBm at 1.1 V. A worst case coupling of 26 dB (45 dB) is measured between adjacent (nonadjacent) elements. The IF bandwidth is 1.2 GHz, limited by the wirebond and PCB interface to the chip. The design occupies only 0.225 mm 2 per element including LO buffer/distribution.